參數(shù)資料
型號(hào)： XRD98L59AIGTR
廠商： Exar Corporation
文件頁(yè)數(shù)： 17/37頁(yè)
文件大?。?/td> 0K
描述： IC CCD DIGITIZER 10BIT 28TSSOP
產(chǎn)品變化通告： Obsolescence Notification 15/Apr/2010
標(biāo)準(zhǔn)包裝： 1,500
位數(shù)： 10
通道數(shù)： 1
電壓 - 電源，模擬： 2.7 V ~ 3.6 V
電壓 - 電源，數(shù)字： 2.7 V ~ 3.6 V
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
XRD98L59
24
Rev. 2.00
Hot Pixel Clipper
CCD’s occasionally have hot pixels. These are defective
pixels which always output a bright level. To ensure the
Black Level is not significantly affected by hot pixels in
the OB area, the Hot Pixel Clipper limits pixel data from
the ADC to a maximum value of 127 (7Fh). The Hot Pixel
Clipper is only active when CAL is active. This clipping
only affects the data used by the internal calibration
logic. Data on the digital output bus DB[9:0] is not
clipped.
Pixel Averager
After the clipper, the logic takes the average of the
Optical Black pixels defined by CAL. This averaging
function filters noise.
Offset Difference Using the Target Offset Register
The Target Offset register (Address 0001) value (6 lsb’s)
is subtracted from the OB pixel average. If the difference
is positive, the offset DACs are decremented to reduce
the effective ADC output code. If the difference is
negative, the offset DACs are adjusted to increase the
effective ADC output code. The amount of adjustment is
shown in Figure 16.
Set the Target Offset Register value equal to the desired
black level output code. For example: Set Target Offset
Register to code 32 and black CCD outputs are nominally
output as 32. Default is code 32 decimal.
Coarse & Fine Accumulators
The Coarse and Fine Accumulators are the registers
which hold the digital codes for the Coarse and Fine
Offset DACs. The Offset DAC adjustments are made by
adding or subtracting to the value in the Fine Accumula-
tor. If there is an overflow or underflow in the Fine
Accumulator, the Fine Accumulator is reset to it’s mid-
scale value, and the Coarse Accumulator is incremented
or decremented accordingly.
CALIBRATION OPTIONS
Speed Up Mode
The purpose of this option is to reduce the amount of time
required for initial convergence of the calibration feed-
back system. The feedback system is designed to have
a slow response time to avoid introducing image arti-
facts. The slow response time is achieved by limiting the
Fine accumulator changes to ± 1 count at a time. The
Speed Up option maintains this slow response while the
difference between the averaged ADC data and the
Target Offset Code is small. But when the difference is
larger than ± 32 lsb’s the Fine accumulator takes large
steps. The actual step size depends on the Gain code,
and is set such that the step will cause no more than a
32 LSB change in the ADC output.
To activate the Speed Up mode write a 1 to the SpeedUp
bit in the Calibration register (bit D3 of Serial Interface
Register #5). By default the SpeedUp mode is active.
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
0
64
128
192
256
PGA Code
ADC
LSB
s
VDD = 3.0V
Figure 16. XRD98L59 Offset DAC Step Size in
ADC Output LSBs
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參數(shù)描述
XRD98L59AIGTR-F 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
XRD98L61 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D
XRD98L61_01 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D
XRD98L61AIV 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D
XRD98L61AIV-F 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel
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