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參數(shù)資料
| 型號(hào)： | XRD98L59AIGTR |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 15/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD DIGITIZER 10BIT 28TSSOP |
| 產(chǎn)品變化通告： | Obsolescence Notification 15/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 1 |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.6 V |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
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XRD98L59
22
Rev. 2.00
The ADC input node can be accesed for test purposes
using the ADCIN mode (SDI address 0100). Use the
following procedure to enable the ADCIN mode:
1) In the Serial interface Clock register, set the
Clamp Opt bit low (D4).
2) In the Serial interface Control register, set the
ADCIN bit high (D2).
3) Clock SBLK & SPIX to generate internal
ADC_CLK signal.
4) Apply ADC input signal to CCDin.
In this test mode the analog signal, Vin, applied to CCDin
pin will be converted by the ADC. The ADC output code
is related to Vin by the following rules:
1)
For Vin < VRB, ADC output code = 0,
2)
For Vin > VRT, ADC output code = 1023,
3)
For VRB < Vin < VRT, ADC output code = 1024
x (Vin - VRB) / (VRT - VRB)
CONTROL & RESET REGISTERS
ADCIN Bit
This bit activates a switch that connects CCDin directly
to the ADC input. In this mode, the PGA output is
disabled. See the ADC section for details.
PD Bit (Power Down)
This bit is used to put the chip in the Power Down mode.
It has the same effect as the PD pin. When the PD bit
is high the chip will go into the power down mode, all
conversions stop. When the PD bit is low the chip is in
its normal active mode. In the Power Down mode the
digital output pins are forced to the high impedance mode
and the ADC reference is disconnected. The serial
interface pins remain active in the Power Down mode.
OE Bit (Output Enable)
The ADC digital output bus is equipped with a high
impedance capability. When the OE bit is high the digital
outputs are enabled (active). When the OE bit is low the
digital outputs are in the high impedance mode (not
active). The OE bit only controls the digital output
drivers, all other circuits on the chip will remain active.
RESET Bit
This bit is used to reset all internal registers to default
values. This includes all the serial interface registers as
well as the registers in the calibration logic. To reset the
chip write a “1” to the reset bit. The reset bit will clear itself
after an internal delay, so there is no need to write a “0”
to the reset bit. The chip also has a Power-On-Reset
function (POR) so it will always power up with default
values in all registers.
It is recommended that the
XRD98L59 be reset after power is cycled to avoid loading
potentially incorrect serial port data from other ASICs in
the system.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| XRD98L59AIGTR-F | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| XRD98L61 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L61_01 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L61AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L61AIV-F | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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