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參數(shù)資料
| 型號： | XRD98L59AIGTR |
| 廠商： | Exar Corporation |
| 文件頁數(shù)： | 13/37頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CCD DIGITIZER 10BIT 28TSSOP |
| 產(chǎn)品變化通告： | Obsolescence Notification 15/Apr/2010 |
| 標(biāo)準(zhǔn)包裝： | 1,500 |
| 位數(shù)： | 10 |
| 通道數(shù)： | 1 |
| 電壓 - 電源，模擬： | 2.7 V ~ 3.6 V |
| 電壓 - 電源，數(shù)字： | 2.7 V ~ 3.6 V |
| 封裝/外殼： | 28-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-TSSOP |
| 包裝： | 帶卷 (TR) |
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XRD98L59
20
Rev. 2.00
Most timing generators (TG’s) define the start of line and
end of line OB pixels on the CCD array. The CAL timing
signal should always be active for the greatest number of
OB pixels possible, either during start or end of line. The
more OB pixels that the XRD98L59 can use for its auto-
calibration, the faster it can achieve and maintain calibra-
tion.
While in “CAL ONLY” Line Calibration Timing Mode,
CLAMP needs to be held inactive during the output of
active video and OB pixels from the CCD. Figure 13
shows the minimum timing requirements for the “CAL
ONLY” Line Calibration Timing Mode. The inactive
state for CLAMP depends on the CLAMP-Polarity
setting (Clock Reg bit D1).
End of Line N
Start of Line N+1
Active Video
Pixels
OB Pixels
Vertical Shift
Dummy &
OB Pixels
CAL
Internal
D C Restore Time
CCD
Si g nal
Active Video Pixels
t
CAL (min 5 Pixels)
4 Pixels
(D1 = 0)
CLAMP
Internal Black Level
Calibration T i m e
t
CAL - 4 Pixels
Figure 13. Example of Minimum Timing Requirements for CAL Only Line Calibration Mode
(CAL and CLAMP Polarity are Serial Port Programmable)
SDI = 0011 0000 0000
Vertical Shift Reject
The CLAMP input can be used to implement a Vertical
Shift Reject function while in “CAL ONLY” Line Cali-
bration Timing Mode. The Vertical Shift Rejection,
also called preblanking, can be used to reject and any
large transients present in the CCD output during the
vertical clocking.
To implement the Vertical Shift Reject (Preblanking)
function on the XRD98L59 the CLAMP opt bit must be
low (Clock Reg D4=0) and the CLAMP input driven
with the preblanking timing signal. The preblanking
timing signal, commonly called PBLK, is generated by
the system timing generator and defines the vertical
shift of the CCD (see Figure 13a). The preblanking
pulse opens the Reset Reject Switches internal to the
XRD98L59, see Figure 5, thereby rejecting any
transients in the CCD output while the vertical shifting
is being done.
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| XRD98L59AIGTR-F | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| XRD98L61 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L61_01 | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L61AIV | 制造商:EXAR 制造商全稱:EXAR 功能描述:CCD Image Digitizers with CDS, PGA and 12-Bit A/D |
| XRD98L61AIV-F | 功能描述:視頻 IC RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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