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| 型號： | XCS05XL-3PQ144I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 61/82頁 |
| 文件大?。?/td> | 623K |
| 代理商： | XCS05XL-3PQ144I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
61
R
Spartan-XL IOB Output Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values are
expressed in nanoseconds unless otherwise noted.
Symbol
Propagation Delays
T
OKPOF
T
OPF
T
TSHZ
T
TSONF
T
OFPF
T
OKFPF
T
SLOW
Setup and Hold Times
T
OOK
T
OKO
T
ECOK
T
OKEC
Global Set/Reset
T
MRW
T
RPO
Description
Device
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Clock (OK) to Pad, fast
Output (O) to Pad, fast
3-state to Pad High-Z (slew-rate independent)
3-state to Pad active and valid, fast
Output (O) to Pad via Output Mux, fast
Select (OK) to Pad via Output Mux, fast
For Output SLOW option add
All devices
All devices
All devices
All devices
All devices
All devices
All devices
-
-
-
-
-
-
-
3.2
2.5
2.8
2.6
3.7
3.3
1.5
-
-
-
-
-
-
-
3.7
2.9
3.3
3.0
4.4
3.9
1.7
ns
ns
ns
ns
ns
ns
ns
Output (O) to clock (OK) setup time
Output (O) to clock (OK) hold time
Clock Enable (EC) to clock (OK) setup time
Clock Enable (EC) to clock (OK) hold time
All devices
All devices
All devices
All devices
0.5
0.0
0.0
0.1
-
-
-
-
0.5
0.0
0.0
0.2
-
-
-
-
ns
ns
ns
ns
Minimum GSR pulse width
Delay from GSR input to any Pad
All devices
XCS05XL
XCS10XL
XCS20XL
XCS30XL
XCS40XL
10.5
-
-
-
-
-
-
11.5
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
11.9
12.4
12.9
13.9
14.9
14.0
14.5
15.0
16.0
17.0
Notes:
1.
Output timing is measured at ~50% V
threshold, with 50 pF external capacitive loads including test fixture. Slew-rate limited output
rise/fall times are approximately two times longer than fast output rise/fall times.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
2.
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| XCS05XL-3PQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS05XL-3PQ256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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