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| 型號： | XCS05XL-3PQ144I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 56/82頁 |
| 文件大?。?/td> | 623K |
| 代理商： | XCS05XL-3PQ144I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
56
www.xilinx.com
1-800-255-7778
DS060 (v1.6) September 19, 2001
Product Specification
R
Spartan-XL CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all Spartan-XL devices and are expressed in nano-
seconds unless otherwise noted.
Symbol
Write Operation
T
WCS
T
WCTS
T
WPS
T
WPTS
T
ASS
T
ASTS
T
DSS
T
DSTS
T
WSS
T
WSTS
Single Port RAM
Size
(1)
Speed Grade
Units
-5
-4
Min
Max
Min
Max
Address write cycle time (clock K period)
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
7.7
7.7
3.1
3.1
1.3
1.5
1.5
1.8
1.4
1.3
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
8.4
8.4
3.6
3.6
1.5
1.7
1.7
2.1
1.6
1.5
0.0
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Clock K pulse width (active edge)
Address setup time before clock K
DIN setup time before clock K
WE setup time before clock K
All hold times after clock K
Data valid after clock K
T
WOS
T
WOTS
Read Operation
T
RC
T
RCT
T
ILO
T
IHO
T
ICK
T
IHCK
Notes:
1.
Timing for 16 x 1 RAM option is identical to 16 x 2 RAM timing.
4.5
5.4
5.3
6.3
Address read cycle time
16x2
32x1
16x2
32x1
16x2
32x1
2.6
3.8
-
-
0.6
1.3
-
-
3.1
5.5
-
-
0.7
1.6
-
-
ns
ns
ns
ns
ns
ns
Data Valid after address change (no Write
Enable)
1.0
1.7
-
-
1.1
2.0
-
-
Address setup time before clock K
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| XCS05XL-3PQ208C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
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| XCS05XL-3PQ240I | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL FPGA |
| XCS05XL-3PQ256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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