參數(shù)資料
型號： XCS05XL-3PQ144I
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列
文件頁數(shù)： 50/82頁
文件大?。?/td> 623K
代理商： XCS05XL-3PQ144I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
50
www.xilinx.com
1-800-255-7778
DS060 (v1.6) September 19, 2001
Product Specification
R
Spartan IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature).
Symbol
Setup Times - TTL Inputs
(1)
Description
Device
Speed Grade
Units
-4
-3
Min
Max
Min
Max
T
ECIK
T
PICK
Hold Times
Clock Enable (EC) to Clock (IK), no delay
All devices
1.6
-
2.1
-
ns
Pad to Clock (IK), no delay
All devices
1.5
-
2.0
-
ns
T
IKEC
Clock Enable (EC) to Clock (IK), no delay
All devices
0.0
-
0.9
-
ns
All Other Hold Times
All devices
0.0
-
0.0
-
ns
Propagation Delays - TTL Inputs
(1)
T
PID
T
PLI
T
IKRI
T
IKLI
Delay Adder for Input with Delay Option
Pad to I1, I2
All devices
-
1.5
-
2.0
ns
Pad to I1, I2 via transparent input latch, no delay
All devices
-
2.8
-
3.6
ns
Clock (IK) to I1, I2 (flip-flop)
All devices
-
2.7
-
2.8
ns
Clock (IK) to I1, I2 (latch enable, active Low)
All devices
-
3.2
-
3.9
ns
T
Delay
T
ECIKD
= T
ECIK
+ T
Delay
T
PICKD
= T
PICK
+ T
Delay
T
PDLI
= T
PLI
+ T
Delay
XCS05
3.6
-
4.0
-
ns
XCS10
3.7
-
4.1
-
ns
XCS20
3.8
-
4.2
-
ns
XCS30
4.5
-
5.0
-
ns
XCS40
5.5
-
5.5
-
ns
Global Set/Reset
T
MRW
T
RRI
Minimum GSR pulse width
All devices
11.5
-
13.5
-
ns
Delay from GSR input to any Q
XCS05
-
9.0
-
11.3
ns
XCS10
-
9.5
-
11.9
ns
XCS20
-
10.0
-
12.5
ns
XCS30
-
10.5
-
13.1
ns
XCS40
-
11.0
-
13.8
ns
Notes:
1.
2.
Delay adder for CMOS Inputs option: for -3 speed grade, add 0.4 ns; for -4 speed grade, add 0.2 ns.
Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input, see the pin-to-pin parameters in the Pin-to-Pin Input Parameters table.
Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
3.
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