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| 型號： | XCS05XL-3PQ144I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 31/82頁 |
| 文件大?。?/td> | 623K |
| 代理商： | XCS05XL-3PQ144I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
31
R
Setting CCLK Frequency
In Master mode, CCLK can be generated in either of two
frequencies. In the default slow mode, the frequency ranges
from 0.5 MHz to 1.25 MHz for Spartan/XL devices. In fast
CCLK mode, the frequency ranges from 4 MHz to 10 MHz
for Spartan/XL devices. The frequency is changed to fast by
an option when running the bitstream generation software.
Data Stream Format
The data stream ("bitstream") format is identical for both
serial configuration modes, but different for the Spartan-XL
Express mode. In Express mode, the device becomes
active when DONE goes High, therefore no length count is
required. Additionally, CRC error checking is not supported
in Express mode. The data stream format is shown in
Table 16
. Bit-serial data is read from left to right. Express
mode data is shown with D0 at the left and D7 at the right.
The configuration data stream begins with a string of eight
ones, a preamble code, followed by a 24-bit length count
and a separator field of ones (or 24 fill bits, in Spartan-XL
Express mode). This header is followed by the actual con-
figuration data in frames. The length and number of frames
depends on the device type (see
Table 17
). Each frame
begins with a start field and ends with an error check. In
serial modes, a postamble code is required to signal the end
of data for a single device. In all cases, additional start-up
bytes of data are required to provide four clocks for the star-
tup sequence at the end of configuration. Long daisy chains
require additional startup bytes to shift the last data through
the chain. All start-up bytes are "don
’
t cares".
Figure 28:
Express Mode Programming Switching Characteristics
DS060_28_080400
BYTE
0
CCLK
FPGA Filled
INIT
T
DC
T
CD
T
IC
D0-D7
DOUT
BYTE
1
BYTE
6
Header Received
Symbol
Description
Min
Max
Units
T
IC
T
DC
T
CD
T
CCH
T
CCL
F
CC
CCLK
INIT (High) setup time
5
-
μ
s
D0-D7 setup time
20
-
ns
D0-D7 hold time
0
-
ns
CCLK High time
45
-
ns
CCLK Low time
45
-
ns
CCLK Frequency
-
10
MHz
Notes:
1.
If not driven by the preceding DOUT, CS1
must
remain High until the
device is fully configured.
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