參數(shù)資料
型號(hào)： XCS05XL-3PQ144I
廠商： Xilinx, Inc.
英文描述： Spartan and Spartan-XL Families Field Programmable Gate Arrays
中文描述： 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù)： 53/82頁(yè)
文件大?。?/td> 623K
代理商： XCS05XL-3PQ144I
Spartan and Spartan-XL Families Field Programmable Gate Arrays
DS060 (v1.6) September 19, 2001
Product Specification
www.xilinx.com
1-800-255-7778
53
R
Spartan-XL DC Characteristics Over Operating Conditions
Supply Current Requirements During Power-On
Spartan-XL FPGAs require that a minimum supply current
I
CCPO
be provided to the V
CC
lines for a successful power
on. If more current is available, the FPGA can consume
more than I
CCPO
min., though this cannot adversely affect
reliability.
A maximum limit for I
CCPO
is not specified. Be careful when
using foldback/crowbar supplies and fuses. It is possible to
control the magnitude of I
CCPO
by limiting the supply current
available to the FPGA. A current limit below the trip level will
avoid inadvertently activating over-current protection cir-
cuits.
Symbol
Description
Min
Typ.
Max
Units
V
OH
High-level output voltage @ I
OH
=
–
4.0 mA, V
CC
min (LVTTL)
High-level output voltage @ I
OH
=
–
500
μ
A, (LVCMOS)
Low-level output voltage @ I
OL
= 12.0 mA, V
CC
min (LVTTL)
(1)
Low-level output voltage @ I
OL
= 24.0 mA, V
CC
min (LVTTL)
(2)
Low-level output voltage @ I
OL
= 1500
μ
A, (LVCMOS)
Data retention supply voltage (below which configuration data
may be lost)
Quiescent FPGA supply current
(3,4)
2.4
-
-
V
90% V
CC
-
-
-
V
V
OL
-
0.4
V
-
-
0.4
V
-
-
10% V
CC
-
V
V
DR
2.5
-
V
I
CCO
Commercial
-
0.1
2.5
mA
Industrial
-
0.1
5
mA
I
CCPD
Power Down FPGA supply current
(3,5)
Commercial
-
0.1
2.5
mA
Industrial
-
0.1
5
mA
I
L
Input or output leakage current
–
10
-
10
μ
A
pF
C
IN
I
RPU
I
RPD
Input capacitance (sample tested)
-
-
10
Pad pull-up (when selected) @ V
IN
= 0V (sample tested)
Pad pull-down (when selected) @ V
IN
= 3.3V (sample tested)
0.02
-
0.25
mA
0.02
-
-
mA
Notes:
1.
2.
3.
4.
5.
With up to 64 pins simultaneously sinking 12 mA (default mode).
With up to 64 pins simultaneously sinking 24 mA (with 24 mA option selected).
With 5V tolerance not selected, no internal oscillators, and the FPGA configured with the Tie option.
With no output current loads, no active input resistors, and all package pins at V
CC
or GND.
With PWRDWN active.
Symbol
I
CCPO
T
CCPO
Notes:
1.
The I
CCPO
requirement applies for a brief time (commonly only a few milliseconds) when V
CC
ramps from 0 to 3.3V.
2.
The ramp time is measured from GND to V
CC
max on a fully loaded board.
3.
V
CC
must not dip in the negative direction during power on.
Description
Min
100
-
Max
-
50
Units
mA
ms
Total V
CC
supply current required during power-on
V
CC
ramp time
(2,3)
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