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| 型號： | XCS05XL-3PQ144I |
| 廠商： | Xilinx, Inc. |
| 英文描述： | Spartan and Spartan-XL Families Field Programmable Gate Arrays |
| 中文描述： | 斯巴達(dá)和Spartan - xL的家庭現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 6/82頁 |
| 文件大?。?/td> | 623K |
| 代理商： | XCS05XL-3PQ144I |
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Spartan and Spartan-XL Families Field Programmable Gate Arrays
6
www.xilinx.com
1-800-255-7778
DS060 (v1.6) September 19, 2001
Product Specification
R
The four internal control signals are:
EC: Enable Clock
SR: Asynchronous Set/Reset or H function generator
Input 0
DIN: Direct In or H function generator Input 2
H1: H function generator Input 1.
Input/Output Blocks (IOBs)
User-configurable input/output blocks (IOBs) provide the
interface between external package pins and the internal
logic. Each IOB controls one package pin and can be con-
figured for input, output, or bidirectional signals.
Figure 6
shows a simplified functional block diagram of the Spar-
tan/XL IOB.
IOB Input Signal Path
The input signal to the IOB can be configured to either go
directly to the routing channels (via I1 and I2 in
Figure 6
) or
to the input register. The input register can be programmed
as either an edge-triggered flip-flop or a level-sensitive
latch. The functionality of this register is shown in
Table 3
,
and a simplified block diagram of the register can be seen in
Figure 5
.
Table 3:
Input Register Functionality
Mode
CK
Power-Up or
GSR
Flip-Flop
0
Latch
1
0
Both
X
Legend:
X
Don
’
t care.
Rising edge (clock not inverted).
SR
Set or Reset value. Reset is default.
0*
Input is Low or unconnected (default
value)
1*
Input is High or unconnected (default
value)
Figure 4:
CLB Control Signal Interface
Multiplexer Controlled
by Configuration Program
C1
DIN
H1
SR
EC
C2
C3
C4
DS060_04_081100
Figure 5:
IOB Flip-Flop/Latch Functional Block
Diagram
EC
X
D
X
Q
SR
X
1*
X
1*
1*
0
D
X
X
D
X
D
Q
Q
D
Q
Multiplexer Controlled
by Configuration Program
D
Q
Q
D
GSR
Vcc
CK
EC
SD
RD
DS060_05_041901
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| XCS05XL-3PQ256C | 制造商:XILINX 制造商全稱:XILINX 功能描述:Spartan and Spartan-XL Families Field Programmable Gate Arrays |
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