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參數(shù)資料
| 型號： | XC17256EPDG8C |
| 廠商： | Xilinx Inc |
| 文件頁數(shù)： | 4/15頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC PROM SERIAL 256K 8-DIP |
| 產(chǎn)品變化通告： | XC1700 PROMs,XC5200,HQ,SCD Parts Discontinuation 19/Jul/2010 Product Discontinuation 28/Jul/2010 |
| 標(biāo)準(zhǔn)包裝： | 50 |
| 可編程類型： | OTP |
| 存儲(chǔ)容量： | 256Kb |
| 電源電壓： | 4.75 V ~ 5.25 V |
| 工作溫度： | 0°C ~ 70°C |
| 封裝/外殼： | 8-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 8-PDIP |
| 包裝： | 管件 |
| 其它名稱： | 122-1576-5 |
12
Device Package User Guide
UG112 (v3.7) September 5, 2012
Chapter 1: Package Information
R
Clockwise or Counterclockwise
The orientation of the die in the package and the orientation of the package on the PC
board affect the PC board layout. PLCC and PQFP packages specify pins in a
counterclockwise direction, when viewed from the top of the package (the surface with the
Xilinx logo). PLCCs have pin 1 in the center of the beveled edge while all other packages
have pin 1 in one corner, with one exception: The 100-pin and 165-pin CQFPs (CB100 and
CB164) for the XC3000 devices have pin 1 in the center of one edge.
CQFP packages specify pins in a clockwise direction, when viewed from the top of the
package. The user can make the pins run counterclockwise by forming the leads such that
the logo mounts against the PC board. However, heat flow to the surrounding air is
impaired if the logo is mounted down.
Cavity-Up or Cavity-Down
Most Xilinx devices attach the die against the inside bottom of the package (the side that
does not carry the Xilinx logo). Called “Cavity-Up,” this has been the standard IC
assembly method for over 25 years. This method does not provide the best thermal
characteristics. Pin Grid Arrays (greater than 130 pins), copper based BGA packages, and
Ceramic Quad Flat Packs are assembled “Cavity-Down,” with the die attached to the
inside top of the package, for optimal heat transfer to the ambient air. More information on
“Cavity-Up” packages and “Cavity-Down” packages can be found in the “Package
Technology Descriptions” section.
For most packages this information does not affect how the package is used because the
user has no choice in how the package is mounted on a board. For Ceramic Quad Flat Pack
(CQFP) packages however, the leads can be formed to either side. Therefore, for best heat
transfer to the surrounding air, CQFP packages should be mounted with the logo up,
facing away from the PC board.
Part Marking
Ordering Information
An example of an ordering code for a Xilinx FPGA is XC4VLX60-10FFG668CS2. The
ordering code stands for:
XC4VLX – Family (Virtex-4 LX)
60 – Number of system gates or logic cells (60,000 logic cells)
-10 – Speed grade (-10 speed)
FFG – Package type (Pb-free flip-chip BGA)
668 – number of pins (668 pins)
C – Temperature grade (Commercial)
S2 – Step 2
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| XC17256EVO8C | 功能描述:IC SERIAL CFG PROM 256K 8-SOIC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲(chǔ)容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
| XC17256EVO8I | 功能描述:IC SERIAL CFG PROM 256K 8-SOIC RoHS:否 類別:集成電路 (IC) >> 存儲(chǔ)器 - 用于 FPGA 的配置 Proms 系列:- 產(chǎn)品變化通告:Product Discontinuation 28/Jul/2010 標(biāo)準(zhǔn)包裝:98 系列:- 可編程類型:OTP 存儲(chǔ)容量:300kb 電源電壓:3 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-TSOP 包裝:管件 |
| XC17256L-PC20C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM |
| XC17256L-PC20I | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Configuration EPROM |
| XC17256LPD8C | 制造商:Xilinx 功能描述: |
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