
VT8231
Preliminary Revision 0.8
October 29, 1999
-
73-
Function 1 Registers - Enhanced IDE Controller
7HFKQRORJLHV,QF
:H &RQQHFW
Offset 4B-48 - Drive Timing Control ............................... RW
The following fields define the Active Pulse Width and
Recovery Time for the IDE DIOR# and DIOW# signals:
31-28 Primary Drive 0 Active Pulse Width
......def=1010b
27-24 Primary Drive 0 Recovery Time
.............def=1000b
23-20 Primary Drive 1 Active Pulse Width
......def=1010b
19-16 Primary Drive 1 Recovery Time
.............def=1000b
15-12 Secondary Drive 0 Active Pulse Width
..def=1010b
11-8 Secondary Drive 0 Recovery Time
.........def=1000b
7-4
Secondary Drive 1 Active Pulse Width
..def=1010b
3-0
Secondary Drive 1 Recovery Time
.........def=1000b
The actual value for each field is the encoded value in the field
plus one and indicates the number of PCI clocks.
Offset 4C - Address Setup Time ...................................... RW
7-6
Primary Drive 0 Address Setup Time
5-4
Primary Drive 1 Address Setup Time
3-2
Secondary Drive 0 Address Setup Time
1-0
Secondary Drive 1 Address Setup Time
For each field above:
00 1T
01 2T
10 3T
11 4T
.....................................................default
Offset 4E - Secondary Non-1F0 Port Access Timing ..... RW
7-4
DIOR#/DIOW# Active Pulse Width
.......def=1111b
3-0
DIOR#/DIOW# Recovery Time
..............def=1111b
The actual value for each field is the encoded value in
the field plus one and indicates the number of PCI
clocks.
Offset 4F - Primary Non-1F0 Port Access Timing` ........ RW
7-4
DIOR#/DIOW# Active Pulse Width
.......def=1111b
3-0
DIOR#/DIOW# Recovery Time
..............def=1111b
The actual value for each field is the encoded value in
the field plus one and indicates the number of PCI
clocks.
Offset 53-50 - UltraDMA Extended Timing Control ..... RW
31
Pri Drive 0 UltraDMA-Mode Enable Method
0
Enable by using
“
Set Feature
”
command.....def
1
Enable by setting bit-30 of this register
30
Pri Drive 0 UltraDMA-Mode Enable
0
Disable...................................................default
1
Enable UltraDMA-Mode Operation
29
Pri Drive 0 Transfer Mode
0
DMA or PIO Mode ...............................default
1
UltraDMA Mode
28-27 Reserved
........................................always reads 0
26-24 Pri Drive 0 Cycle Time (T = 30nsec @33MHz)
000 2T
001 3T
010 4T
011 5T
100 6T
101 7T
110 8T
111 9T
....................................................default
23
22
21
20
19
Pri Drive 1 UltraDMA-Mode Enable Method
Pri Drive 1 UltraDMA-Mode Enable
Pri Drive 1 Transfer Mode
Reserved
........................................always reads 0
Pri Clock Source
0
33 MHz..................................................default
1
66 MHz
18-16 Pri Drive 1 Cycle Time
15
14
13
Sec Drive 0 UltraDMA-Mode Enable Method
Sec Drive 0 UltraDMA-Mode Enable
Sec Drive 0 Transfer Mode
12-11 Reserved
........................................always reads 0
10-8 Sec Drive 0 Cycle Time
7
6
5
4
3
Sec Drive 1 UltraDMA-Mode Enable Method
Sec Drive 1 UltraDMA-Mode Enable
Sec Drive 1 Transfer Mode
Reserved
........................................always reads 0
Sec Clock Source
0
33 MHz..................................................default
1
66 MHz
Sec Drive 1 Cycle Time
Each byte defines UltraDMA operation for the indicated drive.
The bit definitions are the same within each byte.
2-0