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參數(shù)資料
| 型號： | VT8231 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 晶體 |
| 英文描述： | CRYSTAL 8.00MHZ 18PF SMD |
| 中文描述： | 南橋伏特，PC99柔順 |
| 文件頁數(shù)： | 108/132頁 |
| 文件大?。?/td> | 1210K |
| 代理商： | VT8231 |
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VT8231
Preliminary Revision 0.8
October 29, 1999
-
102-
System Management Bus I/O-Space Registers
7HFKQRORJLHV,QF
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I/O Offset 02h
–
SMBus Host Control ............................ RW
7
Reserved
........................................ always reads 0
6
Start
........................................ always reads 0
0
Writing 0 has no effect...........................default
1
Start Execution of Command
Writing a 1 to this bit causes the SMBus
controller host interface to initiate execution of
the command programmed in the SMBus
Command Protocol field (bits 4-2). All
necessary registers should be programmed
prior to writing a 1 to this bit. The Host Busy
bit (SMBus Host Status Register bit-0) can be
used to identify when the SMBus controller
has completed command execution.
5
Reserved
........................................ always reads 0
4-2
SMBus Command Protocol
000 Quick Read or Write ..............................default
001 Byte Read or Write
010 Byte Data Read or Write
011 Word Data Read or Write
100 Reserved
101 Block Read or Write
110 Reserved
111 Reserved
1
Kill Transaction in Progress
0
Normal host controller operation ...........default
1
Stop host transaction currently in progress.
Setting this bit also sets the FAILED status bit
(Host Status bit-4) and asserts the interrupt
selected by the SMB Interrupt Select bit
(Function 4 SMBus Host Configuration
Register RxD2[3]).
0
Interrupt Enable
0
Disable interrupt generation...................default
1
Enable generation of interrupts on completion
of the current host transaction.
I/O Offset 03h
–
SMBus Host Command ....................... RW
7-0
SMBUS Host Command
..........................default = 0
This field contains the data transmitted in the
command field of the SMBus host transaction.
I/O Offset 04h
–
SMBus Host Address............................ RW
The contents of this register are transmitted in the address field
of the SMBus host transaction.
7-1
SMBUS Address
.......................................default = 0
This field contains the 7-bit address of the targeted
slave device.
0
SMBUS Read or Write
0
Execute a WRITE command .................default
1
Execute a READ command
I/O Offset 05h
–
SMBus Host Data 0 .............................. RW
The contents of this register are transmitted in the Data 0 field
of SMBus host transaction writes. On reads, Data 0 bytes are
stored here.
7-0
SMBUS Data 0
..........................................default = 0
For Block Write commands, this field is programmed
with the block transfer count (a value between 1 and
32). Counts of 0 or greater than 32 are undefined.
For Block Read commands, the count received from
the SMBus device is stored here.
I/O Offset 06h
–
SMBus Host Data 1 .............................. RW
The contents of this register are transmitted in the Data 1 field
of SMBus host transaction writes. On reads, Data 1 bytes are
stored here.
7-0
SMBUS Data 1
..........................................default = 0
I/O Offset 07h
–
SMBus Block Data ............................... RW
Reads and writes to this register are used to access the 32-byte
block data storage array. An internal index pointer is used to
address the array. It is reset to 0 by reads of the SMBus Host
Control register (I/O Offset 2) and incremented automatically
by each access to this register. The transfer of block data into
(read) or out of (write) this storage array during an SMBus
transaction always starts at index address 0.
7-0
SMBUS Block Data
..................................default = 0
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