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VT8231
Preliminary Revision 0.8
October 29, 1999
-12-
Pinouts
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Advanced Programmable Interrupt Controller (APIC) Interface
Signal Name
Pin #
I/O
Signal Description
WSC#
/ APICREQ# / GPI14
V4
I / I / I
Internal APIC Write Snoop Complete.
Asserted by the north
bridge to indicate that all snoop activity on the CPU bus initiated
by the last PCI-to-DRAM write is complete and that it is safe to
perform an APIC interrupt.
External APIC Request.
Asserted by external APIC synchronous
to PCICLK prior to sending an interrupt over the APIC serial bus.
This signals the VT8231 to flush its internal buffers.
Internal APIC Data 0.
External APIC Chip Select.
The VT8231 drives this signal active
to select an external APIC (if used). This occurs if the external
APIC is enabled and a PCI cycle is detected within the
programmed APIC address range.
Internal APIC Data 1.
External APIC Acknowledge.
Asserted by the VT8231 to indicate
that it internal buffers have been flushed (in response to
APICREQ#). This indicates to the external APIC that the
VT8231
’
s internal buffers have been flushed and that it is OK for
the APIC to send its interrupt.
APIC Clock.
SCI Out.
Used to route internally generated SCI and SMBus
interrupts to external APIC (if used). Defined as SCIOUT# if
external APIC enabled (function 0 Rx74[7] = 1).
APIC IRQ.
Internal condition for connection to external APIC.
APIC IRQ.
Internal condition for connection to external APIC.
APIC IRQ.
Internal condition for connection to external APIC.
APIC IRQ.
Internal condition for connection to external APIC.
APIC IRQ.
Internal condition for connection to external APIC.
APIC IRQ.
Internal condition for connection to external APIC.
APIC IRQ.
Internal condition for connection to external APIC.
APIC IRQ.
Internal condition for connection to external APIC.
APIC IRQ.
Internal condition for connection to external APIC.
APIC IRQ.
Internal condition for connection to external APIC.
APIC IRQ.
Internal condition for connection to external APIC.
APIC IRQ.
Internal condition for connection to external APIC.
APICD0
/ APICCS# / GPIO28
W4
O / O / IO
APICD1
/ APICACK# / GPIO29
Y4
O / O / IO
APICCLK
/ GPI9
SCIOUT#
/ GPIOD
/ GPIO30 / DTEST
Y3
Y1
I / I
O / IO
IO / O
AIRQ
/ MCOL
AIRQ
/ MCRS
AIRQ
/ MRXCLK
AIRQ
/ MRXD0
AIRQ
/ MRXDV
AIRQ
/ MRXERR
AIRQ
/ MTXCLK
AIRQ
/ MTXD0
AIRQ
/ MTXD1
AIRQ
/ MTXD2
AIRQ
/ MTXD3
AIRQ
/ MTXENA
G17
G16
E17
E19
E20
F18
F16
F20
G18
G19
G20
F19
O
O
O
O
O
O
O
O
O
O
O
O
Serial EEPROM Interface
Signal Name
Pin #
I/O
Signal Description
EECS#
EECK
EEDO
EEDI
C18
E16
C20
C19
O
O
O
I
Serial EEPROM Chip Select.
Serial EEPROM Clock.
Serial EEPROM Data Output.
Serial EEPROM Data Input.