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參數(shù)資料
| 型號(hào)： | VT8231 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類： | 晶體 |
| 英文描述： | CRYSTAL 8.00MHZ 18PF SMD |
| 中文描述： | 南橋伏特，PC99柔順 |
| 文件頁(yè)數(shù)： | 17/132頁(yè) |
| 文件大?。?/td> | 1210K |
| 代理商： | VT8231 |
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VT8231
Preliminary Revision 0.8
October 29, 1999
-11-
Pinouts
7HFKQRORJLHV,QF
:H &RQQHFW
CPU Interface
Signal Name
Pin #
I/O
Signal Description
CPURST
U4
OD
CPU Reset.
The VT8231 asserts CPURST to reset the CPU during
power-up.
CPU Interrupt.
INTR is driven by the VT8231 to signal the CPU that
an interrupt request is pending and needs service.
Non-Maskable Interrupt.
NMI is used to force a non-maskable
interrupt to the CPU. The VT8231 generates an NMI when either
SERR# or IOCHK# is asserted.
Initialization.
The VT8231 asserts INIT if it detects a shut-down
special cycle on the PCI bus or if a soft reset is initiated by the register
Stop Clock.
STPCLK# is asserted by the VT8231 to the CPU to
throttle the processor clock.
System Management Interrupt.
SMI# is asserted by the VT8231 to
the CPU in response to different Power-Management events.
Numerical Coprocessor Error.
This signal is tied to the coprocessor
error signal on the CPU. Internally generates interrupt 13 if active.
Ignore Numeric Error.
This pin is connected to the
“
ignore error
”
pin
on the CPU.
Sleep
(Rx75[7] = 0). Used to put the CPU to sleep. Used with slot-1
CPUs only. Not currently used with socket-7 CPUs.
A20 Mask.
Connect to A20 mask input of the CPU to control address
bit-20 generation. Logical combination of the A20GATE input (from
internal or external keyboard controller) and Port 92 bit-1 (Fast_A20).
CPU DTD (Thermal Diode) Channel Plus.
Connect to cathode of first
external temperature sensing diode.
CPU DTD (Thermal Diode) Channel Minus.
Connect to anode of
first external temperature sensing diode.
INTR
R6
OD
NMI
T5
OD
INIT
V5
OD
STPCLK#
V6
OD
SMI#
Y5
OD
FERR#
U5
I
IGNNE#
T6
OD
SLP#
/ GPO7
U6
OD
A20M#
W5
OD
DTD+
L2
Analog I
DTD-
L3
Analog I
Note: Connect each of the above signals to 4.7K
pullup resistors to VCC3.
Strap Options
Signal Name
Pin #
I/O
Signal Description
Strap
/ SUSA#
P1
I / O
CPURST / INIT Polarity
H:
L:
CPU Frequency Strapping
H: Disable
L: Enable
SD Bus Width
H: 16-Bit
L: 8-Bit
BIO ROM Interface
H: LPC
L: Conventional
Auto Reboot
H: Disable
L: Enable
CPU Type
4.7K to GND = Socket-7, 4.7K to VCC3 = Socket-370 / Slot-1
Strap
/ MCCS#
W6
I / O
Strap
/ PCS0#
Y6
I / O
Strap
/ SA16
Y14
I / IO
Strap
/ SA17
T13
I / IO
Strap
/ KBCS# / ROMCS#
T9
I / O / O
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