參數(shù)資料
型號(hào)： VSC8140
廠商： Vitesse Semiconductor Corporation.
英文描述： 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
中文描述： 2.48832Gb /秒16:1的SONET集成時(shí)鐘發(fā)生器/ SDH的收發(fā)器
文件頁(yè)數(shù)： 9/34頁(yè)
文件大?。?/td> 528K
代理商： VSC8140
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Page 9
9/6/00
VITESSE
Data Sheet
VSC8140
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
G52251-0, Rev. 4.0
When LOOPTIM1 is asserted high, the RXCLK16_32O or RXCLK16O output can be tied to the LPTIM-
CLK input. In order to meet jitter transfer, the RXCLK16_32O or RXCLOCK16O needs to be filtered by a 1X
PLL circuit with a narrow pass characteristic. The part is forced out of this mode in Equipment Loopback to
prevent the PLL from feeding its own clock back.
Clock Generator
An on-chip PLL generates the 2.48832GHz transmit clock from the externally provided REFCLK input.
The on-chip PLL uses a low phase noise reactance-based Voltage Controlled Oscillator (VCO) with an on-chip
loop filter (with two external 0.1
μ
F peaking capacitors). The loop bandwidth of the PLL is within the SONET
specified limit of 2MHz.
The customer can select to provide either a 77.76MHz reference, or 2x of that reference, 155.52MHz.
REF_FREQSEL is used to select the desired reference frequency. REF_FREQSEL = “0” designates REFCLK
input
as 77.76MHz, REF_FREQSEL = “1” designates REFCLK input as 155.52MHz.
The REFCLK should be of high quality since noise on the REFCLK below the loop bandwidth of the PLL
will pass through the PLL and appear as jitter on the output. Preconditioning of the REFCLK signal with a
VCXO may be required to avoid passing REFCLK noise with greater than 2ps RMS of jitter to the output. The
VSC8140 will output the REFCLK noise in addition to the intrinsic jitter from the VSC8140 itself during such
conditions.
Loop Filter
The PLL on the VSC8140 employs an internal loop filter with off-chip peaking capacitors. The PLL design
is fully differential, therefore the loop filter must also be fully differential. One capacitor should be connected
between FILTAO and FILTAI, with the other connected between FILTAON and FILTAIN. Recommended
capacitors are low-inductance 0.1
μ
F 0603 ceramic SMT X7R devices with a voltage rating equal to or greater
than 10V.
Figure 13: High-Speed Output Termination
V
CC
V
EE
Z
0
= 50
50
100
50
Pre-Driver
相關(guān)PDF資料
PDF描述
VSC8140QR 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
VSC8140TW 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
VSC8141 Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VSC8140QR 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
VSC8140TW 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
VSC8141 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator
VSC8141QR 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator
VSC8141TW 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator
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