參數(shù)資料
型號(hào): VSC8140
廠商: Vitesse Semiconductor Corporation.
英文描述: 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
中文描述: 2.48832Gb /秒16:1的SONET集成時(shí)鐘發(fā)生器/ SDH的收發(fā)器
文件頁(yè)數(shù): 20/34頁(yè)
文件大小: 528K
代理商: VSC8140
VITESSE
Data Sheet
VSC8140
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
Page 20
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
9/6/00
G52251-0, Rev. 4.0
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
VEE
I
I
I
I
I
I
I
I
I
I
GND typ.
TTL
TTL
TTL
TTL
TTL
TTL
LVPECL
LVPECL
+3.3V typ.
GND typ.
LVPECL
LVPECL
GND typ.
3.3V typ.
Negative power supply
Facility loopback, active high
Enable internal looptiming operation, active high
Parity mode select
Reset to align FIFO write and read pointers
Enable external loop timing operation, active high
Reference clock input select
External loop timing clock, true
External loop timing clock, complement
Positive power supplys for analog parts of CMU
Negative power supplys for analog parts of CMU
Reference clock input, true
Reference clock input, complement
Negative power supply
Loop filter pin - connect via capacitor to FILTAI (pin 53)
Loop filter pin - connect via capacitor to FILTAIN (pin 54)
Loop filter pin - connect via capacitor to FILTAO (pin 51)
Loop filter pin - connect via capacitor to FILTAON (pin 52)
Positive power supply
Low-speed clock output, true. A divide-by-16 version of the PLL
clock.
Low-speed clock output, complement. A divide-by-16 version of the
PLL clock.
Negative power supply
Low-speed clock input for latching low-speed data, complement
Low-speed clock input for latching low-speed data, true
Positive power supply
Transmitter parity bit input
Low-speed single-ended data (MSB)
(2)
Low-speed single-ended data
Negative power supply
Positive power supply
Low-speed single-ended data
Low-speed single-ended data
Low-speed single-ended data
Low-speed single-ended data
Low-speed single-ended data
FACLOOP
LOOPTIM0
PARMODE
FIFORESET
LOOPTIM1
REF_FREQSEL
LPTIMCLK+
LPTIMCLK-
VCC_ANA
VEE_ANA
REFCLK+
REFCLK-
VEE
FILTAO
FILTAON
FILTAI
FILTAIN
VCC
56
TXCLK16O+
O
LVPECL
57
TXCLK16O-
O
LVPECL
58
59
60
61
62
63
64
65
66
67
68
69
70
71
VEE
I
I
I
I
I
I
I
I
I
I
GND typ.
LVPECL
LVPECL
3.3V typ.
LVPECL
LVPECL
LVPECL
GND typ.
3.3V typ.
LVPECL
LVPECL
LVPECL
LVPECL
LVPECL
TXCLK16I-
TXCLK16I+
VCC
TXPARITYIN
TXIN15
TXIN14
VEE
VCC
TXIN13
TXIN12
TXIN11
TXIN10
TXIN9
Table 4: Package Pin Identification - 128 PQFP
Pin #
Name
I/O
Level
Description
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
VSC8140QR 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
VSC8140TW 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
VSC8141 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator
VSC8141QR 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator
VSC8141TW 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator