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參數(shù)資料
| 型號： | VSC8140 |
| 廠商： | Vitesse Semiconductor Corporation. |
| 英文描述： | 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| 中文描述： | 2.48832Gb /秒16:1的SONET集成時(shí)鐘發(fā)生器/ SDH的收發(fā)器 |
| 文件頁數(shù)： | 25/34頁 |
| 文件大小： | 528K |
| 代理商： | VSC8140 |
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VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
Page 25
9/6/00
VITESSE
Data Sheet
VSC8140
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
G52251-0, Rev. 4.0
B3
VCC
—
3.3V typ.
Positive power supply
D4
VCC
—
3.3V typ.
Positive power supply
C3
VEE
—
GND typ.
Negative power supply
C1
FACLOOP
I
TTL
Facility loopback, active high
F4
LOOPTIM0
I
TTL
Enable internal looptiming operation, active high
F3
PARMODE
I
TTL
Parity mode select
D1
FIFORESET
I
TTL
Reset to align FIFO write and read pointers
E1
LOOPTIM1
I
TTL
Enable external loop timing operation, active high
G4
REF_FREQSEL
I
TTL
Reference clock input select
G3
VEE
—
GND typ.
Negative power supply
F2
LPTIMCLK+
I
LVPECL
External loop timing clock, true
G2
LPTIMCLK-
I
LVPECL
External loop timing clock, complement
F1
VCC_ANA
—
+3.3V typ.
Positive power supplies for analog parts of CMU
H3
VEE_ANA
—
GND typ.
Negative power supplies for analog parts of CMU
H2
REFCLK+
I
LVPECL
Reference clock input, true
G1
REFCLK-
I
LVPECL
Reference clock input,complement
H1
VEE
—
GND typ.
Negative power supply
J2
VCC
—
3.3V typ.
Positive power supply
J4
FILTAO
—
—
Loop filter pin - connect via capacitor to FILTAI (pin 53)
J3
FILTAON
—
—
Loop filter pin - connect via capacitor to FILTAIN (pin 54)
K1
FILTAI
—
—
Loop filter pin - connect via capacitor to FILTAO (pin 51)
K2
FILTAIN
—
—
Loop filter pin - connect via capacitor to FILTAON (pin 52)
K3
VCC
—
3.3V typ.
Positive power supply
K4
TXCLK16O+
O
LVPECL
Low-speed clock output, true. A divide-by-16 version of the PLL
clock.
L1
TXCLK16O-
O
LVPECL
Low-speed clock output, complement. A divide-by-16 version of the
PLL clock.
M1
VEE
—
GND typ.
Negative power supply
L2
TXCLK16I-
I
LVPECL
Low-speed clock input for latching low-speed data, complement
L3
TXCLK16I+
I
LVPECL
Low-speed clock input for latching low-speed data, true
L4
VCC
—
3.3V typ.
Positive power supply
M2
TXPARITYIN
I
LVPECL
Transmitter parity bit input
Low-speed single-ended data (MSB)
(1)
M3
TXIN15
I
LVPECL
M4
TXIN14
I
LVPECL
Low-speed single-ended data
P1
VEE
—
GND typ.
Negative power supply
Table 5: Package Pin Identification - 208 BGA
Pin #
Name
I/O
Level
Description
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| VSC8140QR | 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| VSC8140QR | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| VSC8140TW | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| VSC8141 | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| VSC8141QR | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
| VSC8141TW | 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator |
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