參數(shù)資料
型號(hào): VSC8140
廠商: Vitesse Semiconductor Corporation.
英文描述: 2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
中文描述: 2.48832Gb /秒16:1的SONET集成時(shí)鐘發(fā)生器/ SDH的收發(fā)器
文件頁數(shù): 16/34頁
文件大?。?/td> 528K
代理商: VSC8140
VITESSE
Data Sheet
VSC8140
2.48832Gb/s 16:1 SONET/SDH
Transceiver with Integrated Clock Generator
Page 16
VITESSE
SEMICONDUCTOR CORPORATION
741 Calle Plano, Camarillo, CA 93012 805/388-3700 FAX: 805/987-5896
9/6/00
G52251-0, Rev. 4.0
Figure 22: Receiver AC Timing Waveforms
Figure 23: Receiver Setup and Hold Time Requirements
Table 2: Receiver AC Characteristics
Parameters
Description
Min
Typ
Max
Units
Conditions
t
RXPDD
Data valid from falling edge of
RXCLK16O+
RXCLK32O transition from
falling edge of RXCLK16O+
RXOUT[15:0]+/- rise and fall
times
RXCLK16O+/- rise and fall
times
RXCLK16O+/- duty cycle
distortion
RXIN+ setup time with respect
to falling edge of RXCLKIN+
RXIN+ hold time with
respect to falling edge of
RXCLKIN+
RXCLKIN+/- duty cycle
distortion
0
800
ps
t
RXPD32
0
1.0
ns
t
RXDR
, t
RXDF
300
ps
20% to 80% into DC termination.
See Figure 24.
20% to 80% into 100
load.
See Figure 24.
High-speed clock input at
2.48832GHz.
t
RXCLKR
,
t
RXCLKF
250
ps
RXCLK16O
D
45
55
% of
clock cycle
t
RXDSU
100
ps
t
RXDH
75
ps
RXCLKIN
D
40
60
% of
clock cycle
t
RXDSU
t
RXPDD
t
RXPD32
Valid Data 1
RXCLK16O+
Parallel Data Clock Output
RXOUT[0:15]+
Parallel Data Outputs
RXCLK32O+
Parallel Data Clock Output
= don’t care
Valid Data 2
D15
MSB
LSB
Time
D14
D13
RXIN+
Differential Serial Data Input
RXCLKIN+
Differential Clock Input
NOTE: Bit 15 (MSB) is received first, Bit 0 (LSB) is received last.
t
RXDSU
t
RXDH
D1
D0
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VSC8140QR 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:2.48832Gb/s 16:1 SONET/SDH Transceiver with Integrated Clock Generator
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VSC8141TW 制造商:VITESSE 制造商全稱:Vitesse Semiconductor Corporation 功能描述:Multi-Rate 16:1 SONET/SDH Transceiver with Integrated Clock Generator