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SMSC DS – USB97C201
Page 37
Rev. 03/25/2002
PRELIMINARY
NAK
(0xD7 - RESET=0x00)
NAME
NAK2RX
NAK REGISTER
DESCRIPTION
BIT
4
R/W
R
1 = indicates that an NAK has been sent to the host on
Endpoint 2 in response to an OUT token.
1 = indicates that an NAK has been sent to the host on
Endpoint 1 in response to an IN token.
1 = indicates that an NAK has been sent to the host on
Endpoint 1 in response to an OUT token.
1 = indicates that an NAK has been sent to the host on
Endpoint 0 in response to an IN token.
1 = indicates that an NAK has been sent to the host on
Endpoint 0 in response to an OUT token.
3
NAK1TX
R
2
NAK1RX
R
1
NAK0TX
R
0
NAK0RX
R
Notes:
Any bit that is high in this register, if not masked by the corresponding mask bit in the NAK_MSK register will
generate INT5 to the 8051.
A bit in this register may be cleared by writing a “1” to it.
Table 49 – NAK Mask Register
NAK_MSK
(0xD9- RESET=0xFF)
NAME
NYET2RX
NAK MASK REGISTER
DESCRIPTION
BIT
7
R/W
R/W
1 = Prevents generation of the 8051 INT5 interrupt when the
NYET2RX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NYET0RX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NAK2TX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NAK2RX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NAK1TX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NAK1RX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NAK0TX bit is set in the NAK register.
1 = Prevents generation of the 8051 INT5 interrupt when the
NAK0RX bit is set in the NAK register.
6
NYET0RX
R/w
5
NAK2TX
R/W
4
NAK2RX
R/W
3
NAK1TX
R/W
2
NAK1RX
R/W
1
NAK0TX
R/W
0
NAK0RX
R/W
Table 50 – USB Error Register
USB_ERR
(0xDA - RESET=0x00)
NAME
Reserved
TOKEN
USB ERROR REGISTER
DESCRIPTION
BIT
7
6
R/W
R
R/W
This bit always reads a “0”.
When set, this bit indicates that an unexpected token has
been received on one of the device’s endpoints.
This bit always reads a “0”.
When set, indicates that a token has been received on a
endpoint of the device while that endpoint is in the STALL
condition.
When set, indicates that a data packet has been received
on one of the device’s endpoints that has an incorrect data
toggle.
When set, indicates that a packet has been received on one
of the device’s endpoint with an error in FS mode.
This bit always reads a “0”.
When set, indicates that a packet with an incorrect CRC
5
4
Reserved
STALL
R
R/W
3
DTOG
R/W
2
RXERR
R/W
1
0
Reserved
CRC
R
R/W