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參數(shù)資料
| 型號(hào)： | USB97C201-MN |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | USB 2.0 ATA/ ATAPI Controller |
| 中文描述： | UNIVERSAL SERIAL BUS CONTROLLER, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁數(shù)： | 32/59頁 |
| 文件大?。?/td> | 385K |
| 代理商： | USB97C201-MN |
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SMSC DS – USB97C201
Page 32
Rev. 03/25/2002
PRELIMINARY
Table 30 – USB Configuration Number Register
USB_CONF
(0xAD - RESET=0x00)
NAME
Reserved
CONFIG
USB CONFIGURATION NUMBER REGISTER
DESCRIPTION
Always returns a “0”.
Reflects
the
current
configuration
USB97C201 system as set by the host.
BIT
[7:4]
{3:0}
R/W
R
R
number
of
the
Table 31 – Endpoint 0 Receive Control Register
EP0RX_CTL
(0xAF - RESET=0x00)
NAME
R/W
Reserved
R
This bit always reads “0”.
ENDPOINT 0 RECEIVE CONTROL REGISTER
DESCRIPTION
BIT
[7:4]
3
DTOG
R
This bit reflects the data toggle state of the last received
data token.
When set to a “1”, EP0 will respond with the STALL
handshake to OUT tokens EXCEPT a SETUP, which it will
ACK unconditionally. Either the internal SIE or the user may
set this bit. Receipt of a SETUP packet or USB RESET
clears this bit. Writing a “0” to this bit has no effect.
This bit always reads “0”.
Reads 1 if EP0 Receive is enabled by SIE.
2
STALL
R/W
1
0
Reserved
ENABLE
R
R
Table 32 – Endpoint 0 Transmit Control Register
EP0TX_CTL
(0xB1 - RESET=0x00)
NAME
R/W
Reserved
R
This bit always reads “0”.
Reserved
R
This bit always reads “0”.
Reserved
R
This bit always reads “0”.
TX
R/W
When written with a “1”, allows the SIE to transfer data from
the buffer SRAM to EP0. OUT tokens will be NAK’d until the
transfer has been completed. It is cleared by the SIE when
transmission of the packet has been completed.
Reserved
R
This bit always reads “0”.
STALL
R/W
When set to a “1”, EP0 TX will respond with the STALL
handshake to IN tokens. . Either the internal SIE or the user
may set this bit. Receipt of a SETUP packet or USB RESET
clears this bit. Writing a “0” to this bit has no effect.
Reserved
R
This bit always reads “0”.
ENABLE
R
Reads “1” if EP0 Transmit is enabled by the SIE.
ENDPOINT 0 TRANSMIT CONTROL REGISTER
DESCRIPTION
BIT
7
6
5
4
3
2
1
0
Table 33 – Endpoint 1 Receive Control Register
EP1RX_CTL
(0xB2 - RESET=0x00)
NAME
R/W
Reserved
R
This bit always reads “0”.
ENDPOINT 1 RECEIVE CONTROL REGISTER
DESCRIPTION
BIT
[7:4]
3
DTOG
R
This bit reflects the data toggle state of the last received
data token.
When set to a “1”, EP1 RX will respond with the STALL
handshake to OUT tokens. . Either the internal SIE or the
user may set this bit. Receipt of a “CLEAR FEATURE
ENDPOINT CLEAR” command for this endpoint or USB
2
STALL
R/W
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PDF描述 |
|---|---|
| USB97CFDC-MN | USB FLOPPY DISK CONTROLLER |
| USB97C202 | ATA/ATAPI CONTROLLER |
| USB97C202-MN-02 | ATA/ATAPI CONTROLLER |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| USB97C202 | 制造商:SMSC 制造商全稱:SMSC 功能描述:USB 2.0 ATA/ATAPI Controller |
| USB97C202_07 | 制造商:SMSC 制造商全稱:SMSC 功能描述:USB 2.0 ATA/ATAPI Controller |
| USB97C202-MN-02 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| USB97C202-MN-04 | 制造商:Rochester Electronics LLC 功能描述:USB 2.0 ATA/ATAPI PERI CNTRLR - Bulk |
| USB97C202-MN-05 | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
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