參數資料
型號: USB3450-FZG
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE
中文描述: SERIAL COMM CONTROLLER, QCC40
封裝: 6 X 6 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MO-220, QFN-40
文件頁數: 31/40頁
文件大?。?/td> 1086K
代理商: USB3450-FZG
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
7.7
SMSC USB3450
31
Revision 0.1 (05-11-05)
DATASHEET
HS Detection Handshake
The High Speed Detection Handshake process is entered from one of three states: suspend, active
FS or active HS. The downstream facing port asserting an SE0 state on the bus initiates the HS
Detection Handshake. Depending on the initial state, an SE0 condition can be asserted from 0 to 4
ms before initiating the HS Detection Handshake. These states are described in the Hi-Speed
specification.
There are three ways in which a device may enter the HS Handshake Detection process:
1. If the device is suspended and it detects an SE0 state on the bus it may immediately enter the HS
handshake detection process.
2. If the device is in FS mode and an SE0 state is detected for more than 2.5μs. it may enter the HS
handshake detection process.
3. If the device is in HS mode and an SE0 state is detected for more than 3.0ms. it may enter the
HS handshake detection process. In HS mode, a device must first determine whether the SE0 state
is signaling a suspend or a reset condition. To do this the device reverts to FS mode by placing
XCVRSELECT and TERMSELECT into FS mode. The device must not wait more than 3.125ms
before the reversion to FS mode. After reverting to FS mode, no less than 100μs and no more
than 875μs later the Link must check the LINESTATE signals. If a J state is detected the device
will enter a suspend state. If an SE0 state is detected, then the device will enter the HS Handshake
detection process.
In each case, the assertion of the SE0 state on the bus initiates the reset. The minimum reset interval
is 10ms. Depending on the previous mode that the bus was in, the delay between the initial assertion
of the SE0 state and entering the HS Handshake detection can be from 0 to 4ms.
This transceiver design pushes as much of the responsibility for timing events on to the Link as
possible, and the Link requires a stable CLKOUT signal to perform accurate timing. In case 2 and 3
above, CLKOUT has been running and is stable, however in case 1 the USB3450 is reset from a
suspend state, and the internal oscillator and clocks of the transceiver are assumed to be powered
down. A device has up to 6ms after the release of SUSPENDN to assert a minimum of a 1ms Chirp K.
7.8
HS Detection Handshake – FS Downstream Facing Port
Upon entering the HS Detection process (T0) XCVRSELECT and TERMSELECT are in FS mode. The
DP pull-up is asserted and the HS terminations are disabled. The Link then sets OPMODE to
Disable
Bit Stuffing and NRZI encoding
, XCVRSELECT to HS mode, and begins the transmission of all 0's
data, which asserts a HS K (chirp) on the bus (T1). The device chirp must last at least 1.0ms, and
must end no later than 7.0ms after HS Reset T0. At time T1 the device begins listening for a chirp
sequence from the host port.
If the downstream facing port is not HS capable, then the HS K asserted by the device is ignored and
the alternating sequence of HS Chirp K’s and J’s is not generated. If no chirps are detected (T4) by
the device, it will enter FS mode by returning XCVRSELECT to FS mode.
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