- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄383985 > USB3450-FZG (STANDARD MICROSYSTEMS CORP) HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE PDF資料下載
參數(shù)資料
| 型號： | USB3450-FZG |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE |
| 中文描述： | SERIAL COMM CONTROLLER, QCC40 |
| 封裝： | 6 X 6 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MO-220, QFN-40 |
| 文件頁數(shù)： | 21/40頁 |
| 文件大?。?/td> | 1086K |
| 代理商： | USB3450-FZG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
6.2
SMSC USB3450
21
Revision 0.1 (05-11-05)
DATASHEET
TX Logic
This block receives parallel data bytes placed on the DATA bus and performs the necessary transmit
operations. These operations include parallel to serial conversion, bit stuffing and NRZI encoding.
Upon valid assertion of the proper TX control lines by the Link and TX State Machine, the TX LOGIC
block will synchronously shift, at either the FS or HS rate, the data to the FS/HS TX block to be
transmitted on the USB cable. Data transmit timing is shown in
Figure 6.3
.
The behavior of the Transmit State Machine is described below.
■
The Link asserts TXVALID to begin a transmission.
■
After the Link asserts TXVALID it can assume that the transmission has started when it detects
TXREADY has been asserted.
■
The Link must assume that the USB3450 has consumed a data byte if TXREADY and TXVALID
are asserted on the rising edge of CLKOUT.
■
The Link must have valid packet information (PID) asserted on the DATA bus coincident with the
assertion of TXVALID.
■
TXREADY is sampled by the Link on the rising edge of CLKOUT.
■
The Link negates TXVALID to complete a packet. Once negated, the transmit logic will never
reassert TXREADY until after the EOP has been generated. (TXREADY will not re-assert until
TXVALD asserts again.
■
The USB3450 is ready to transmit another packet immediately, however the Link must conform to
the minimum inter-packet delays identified in the Hi-Speed specification.
■
Supports high speed disconnect detect through the HOSTDISC pin. In Host mode the USB3450
will sample the disconnect comparator at the 32nd bit of the 40 bit long EOP during SOF packets.
■
Supports FS pre-amble for FS hubs with a LS device.
■
Supports LS keep alive by receiving the SOF PID.
■
Supports Host mode resume K which ends with two low speed times of SE0 followed by 1 FS “J”.
6.3
RX Logic
This block receives serial data from the clock recovery circuits and processes it to be transferred to
the Link on the DATA bus. The processing involved includes NRZI decoding, bit unstuffing, and serial
to parallel conversion. Upon valid assertion of the proper RX control lines, the RX Logic block will
provide bytes to the DATA bus as shown in the figures below. The behavior of the receiver is described
below.
Figure 6.3 Transmit Timing for a Data Packet
相關PDF資料 |
PDF描述 |
|---|---|
| USB97C201 | USB 2.0 ATA/ ATAPI Controller |
| USB97C201-MC | USB 2.0 ATA/ ATAPI Controller |
| USB97C201-MN | USB 2.0 ATA/ ATAPI Controller |
| USB97CFDC-MN | USB FLOPPY DISK CONTROLLER |
| USB97C202 | ATA/ATAPI CONTROLLER |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| USB-3488A | 功能描述:數(shù)據(jù)記錄與采集 HIGH PERF IEEE-488 USB DAQ GPIB INT CON RoHS:否 制造商:Lantronix 描述/功能:Analog device server 顯示器類型:None 電流額定值: |
| USB3500 | 制造商:SMSC 制造商全稱:SMSC 功能描述:Hi-Speed USB Host, Device or OTG PHY With UTMI+ Interface |
| USB3500-ABZJ | 功能描述:接口 - 專用 USB 2.0 PHY UTMI RoHS:否 制造商:Texas Instruments 產(chǎn)品類型:1080p60 Image Sensor Receiver 工作電源電壓:1.8 V 電源電流:89 mA 最大功率耗散: 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:BGA-59 |
| USB3503 | 制造商:SMSC 制造商全稱:SMSC 功能描述:USB 2.0 HSIC High-Speed Hub Controller Optimized for Portable Applications |
| USB3503A | 制造商:SMSC 制造商全稱:SMSC 功能描述:USB 2.0 HSIC High-Speed Hub Controller Optimized for Portable Applications |
發(fā)布緊急采購，3分鐘左右您將得到回復。