參數(shù)資料
型號(hào)： USB3450-FZG
廠商： STANDARD MICROSYSTEMS CORP
元件分類： 微控制器/微處理器
英文描述： HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE
中文描述： SERIAL COMM CONTROLLER, QCC40
封裝： 6 X 6 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MO-220, QFN-40
文件頁數(shù)： 22/40頁
文件大小： 1086K
代理商： USB3450-FZG
Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
Revision 0.1 (05-11-05)
22
SMSC USB3450
DATASHEET
The assertion of RESET will cause the USB3450 to deasserts RXACTIVE and RXVALID. When the
RESET signal is deasserted the Receive State Machine starts looking for a SYNC pattern on the USB.
When a SYNC pattern is detected the receiver will assert RXACTIVE. The length of the received Hi-
Speed SYNC pattern varies and can be up to 32 bits long or as short as 12 bits long when at the end
of five hubs.
After valid serial data is received, the data is loaded into the RX Holding Register on the rising edge
of CLKOUT and RXVALID is asserted. The Link must clock the data off the DATA bus on the next
rising edge of CLKOUT. In normal mode (OPMODE = 00), then stuffed bits are stripped from the data
stream. Each time 8 stuffed bits are accumulated the USB3450 will negate RXVALID for one clock
cycle, thus skipping a byte time.
When the EOP is detected the USB3450 will negate RXACTIVE and RXVALID. After the EOP has
been stripped the USB3450 will begin looking for the next packet.
The behavior of the USB3450 receiver is described below:
■
RXACTIVE and RXREADY are sampled on the rising edge of CLKOUT.
■
After a EOP is complete the receiver will begin looking for SYNC.
■
The USB3450 asserts RXACTIVE when SYNC is detected.
■
The USB3450 negates RXACTIVE when an EOP is detected and the elasticity buffer is empty.
■
When RXACTIVE is asserted, RXVALID will be asserted if the RX Holding Register is full.
■
RXVALID will be negated if the RX Holding Register was not loaded during the previous byte time.
This will occur if 8 stuffed bits have been accumulated.
■
The Link must be ready to consume a data byte if RXACTIVE and RXVALID are asserted (RX Data
state).
■
Figure 6.5
shows the timing relationship between the received data (DP/DM), RXVALID,
RXACTIVE, RXERROR and DATA signals.
Notes:
■
Figure 6.5
,
Figure 6.6
and
Figure 6.7
are timing examples of a HS/FS PHY when it is in HS mode.
When a HS/FS PHY is in FS Mode there are approximately 40 CLKOUT cycles every byte time.
The Receive State Machine assumes that the Link captures the data on the DATA bus if RXACTIVE
and RXVALID are asserted. In FS mode, RXVALID will only be asserted for one CLKOUT per byte
time.
■
In
Figure 6.5
,
Figure 6.6
and
Figure 6.7
the SYNC pattern on DP/DM is shown as one byte long.
The SYNC pattern received by a device can vary in length. These figures assume that all but the
last 12 bits have been consumed by the hubs between the device and the host controller.
Figure 6.4 Receive Timing for Data with Unstuffed Bits
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