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參數(shù)資料
| 型號(hào)： | USB3450-FZG |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | HI-SPEED USB HOST OR DEVICE PHY WITH UTMI+INTERFACE |
| 中文描述： | SERIAL COMM CONTROLLER, QCC40 |
| 封裝： | 6 X 6 MM, 0.90 MM HEIGHT, 0.50 MM PITCH, ROHS COMPLIANT, MO-220, QFN-40 |
| 文件頁數(shù)： | 11/40頁 |
| 文件大小： | 1086K |
| 代理商： | USB3450-FZG |
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Hi-Speed USB Host or Device PHY With UTMI+ Interface
Datasheet
3.2
SMSC USB3450
11
Revision 0.1 (05-11-05)
DATASHEET
Pin Definitions
Table 3.1 USB3450 Pin Definitions
PIN
NAME
DIRECTION,
TYPE
ACTIVE
LEVEL
DESCRIPTION
1
XCVRSEL[0]
Input
N/A
Transceiver Select. These signals select between
the FS and HS transceivers:
Transceiver select.
00: HS
01: FS
10: LS
11: LS data, FS rise/fall times
2
TERMSEL
Input
N/A
Termination Select. This signal selects between the
FS and HS terminations:
0: HS termination enabled
1: FS termination enabled
3
TXREADY
Output
High
Transmit Data Ready. If TXVALID is asserted, the
Link must always have data available for clocking
into the TX Holding Register on the rising edge of
CLKOUT. TXREADY is an acknowledgement to the
Link that the transceiver has clocked the data from
the bus and is ready for the next transfer on the bus.
If TXVALID is negated, TXREADY can be ignored by
the Link.
4
SUSPENDN
Input
Low
Suspend. Places the transceiver in a mode that
draws minimal power from supplies. In host mode,
R
PU
is removed during suspend. In device mode,
R
is controlled by TERMSEL. In suspend mode
the clocks are off.
0: PHY in suspend mode
1: PHY in normal operation
5
TXVALID
Input
High
Transmit Valid. Indicates that the DATA bus is valid
for transmit. The assertion of TXVALID initiates the
transmission of SYNC on the USB bus. The
negation of TXVALID initiates EOP on the USB.
Control inputs (OPMODE[1:0],
TERMSEL,XCVERSEL) must not be changed on the
de-assertion or assertion of TXVALID.
6
RESET
Input
High
Reset. Reset all state machines. After coming out
of reset, must wait 5 rising edges of clock before
asserting TXValid for transmit.
Assertion of Reset: May be asynchronous to
CLKOUT
De-assertion of Reset: Must be synchronous to
CLKOUT
7
VDD3.3
N/A
N/A
3.3V PHY Supply. Provides power for Hi-Speed
Transceiver, UTMI+ Digital, Digital I/O, and
Regulators.
8
DP
I/O,
Analog
N/A
D+ pin of the USB cable.
9
DM
I/O,
Analog
N/A
D- pin of the USB cable.
10
NC
N/A
N/A
No Connect.
11
VDD3.3
N/A
N/A
3.3V PHY Supply.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| USB-3488A | 功能描述:數(shù)據(jù)記錄與采集 HIGH PERF IEEE-488 USB DAQ GPIB INT CON RoHS:否 制造商:Lantronix 描述/功能:Analog device server 顯示器類型:None 電流額定值: |
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