參數(shù)資料
型號(hào): UPSD3253B-40T6
廠商: STMICROELECTRONICS
元件分類(lèi): 微控制器/微處理器
英文描述: 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP52
封裝: PLASTIC, TQFP-52
文件頁(yè)數(shù): 41/189頁(yè)
文件大?。?/td> 1638K
代理商: UPSD3253B-40T6
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Obsolete
Product(s)
- Obsolete
Product(s)
UPSD3254A, UPSD3254BV, UPSD3253B, UPSD3253BV
I/O ports (PSD module)
Figure 61.
General I/O port architecture
The Port pin’s tri-state output driver enable is controlled by a two input OR gate whose
inputs come from the CPLD AND Array enable product term and the Direction Register. If
the enable product term of any of the Array outputs are not defined and that port pin is not
defined as a CPLD output in the PSDsoft, then the Direction Register has sole control of the
buffer that drives the port pin.
The contents of these registers can be altered by the MCU. The Port Data Buffer (PDB)
feedback path allows the MCU to check the contents of the registers.
Ports A, B, and C have embedded Input Macrocells (IMC). The Input Macrocells (IMC) can
be configured as latches, registers, or direct inputs to the PLDs. The latches and registers
are clocked by Address Strobe (ALE) or a product term from the PLD AND Array. The
outputs from the Input Macrocells (IMC) drive the PLD input bus and can be read by the
MCU. See Figure 60.
24.2
Port operating modes
The I/O Ports have several modes of operation. Some modes can be defined using PSDsoft,
some by the MCU writing to the Control Registers in CSIOP space, and some by both. The
modes that can only be defined using PSDsoft must be programmed into the device and
cannot be changed unless the device is reprogrammed. The modes that can be changed by
the MCU can be done so dynamically at run-time. The PLD I/O, Data Port, Address Input,
and Peripheral I/O modes are the only modes that must be defined before programming the
device. All other modes can be changed by the MCU at run-time. See Application Note
AN1171 for more detail.
Table 93 summarizes which modes are available on each port. Table 96 shows how and
where the different modes are configured. Each of the port operating modes are described
in the following sections.
MCU
DATA
BUS
DATA OUT
REG.
DQ
D
G
Q
DQ
WR
ADDRESS
MACROCELL OUTPUTS
ENABLE PRODUCT TERM (.OE)
EXT CS
ALE
READ MUX
P
D
B
CPLD - INPUT
CONTROL REG.
DIR REG.
INPUT
MACROCELL
ENABLE OUT
DATA IN
OUTPUT
SELECT
OUTPUT
MUX
PORT PIN
DATA OUT
ADDRESS
AI06604
相關(guān)PDF資料
PDF描述
UPSD3334D-40U6 8-BIT, FLASH, 40 MHz, MICROCONTROLLER, PQFP80
US1001FL 0.5 A, 100 V, SILICON, SIGNAL DIODE
US1A-HE3 1 A, 50 V, SILICON, SIGNAL DIODE, DO-214AC
US1B-HE3 1 A, 100 V, SILICON, SIGNAL DIODE, DO-214AC
US1G-HE3 1 A, 400 V, SILICON, SIGNAL DIODE, DO-214AC
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參數(shù)描述
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