CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00
User’s Manual U16315EJ3V1UD
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(8) Timer operation
<1>
Even if 16-bit timer counter 00 (TM00) is read, the value is not captured by 16-bit timer capture/compare
register 010 (CR010).
<2>
Regardless of the CPU’s operation mode, when the timer stops, the input signals to the TI000/TI010 pins
are not acknowledged.
<3>
The one-shot pulse output mode operates correctly only in the free-running mode and the mode in which
clear & start occurs at the TI000 valid edge. In the mode in which clear & start occurs on a match between
the TM00 register and CR000 register, one-shot pulse output is not possible because an overflow does not
occur.
(9) Capture operation
<1>
If TI000 valid edge is specified as the count clock, a capture operation by the capture register specified as
the trigger for TI000 is not possible.
<2>
To ensure the reliability of the capture operation, the capture trigger requires a pulse longer than two cycles
of the count clock selected by prescaler mode register 00 (PRM00).
<3>
The capture operation is performed at the falling edge of the count clock.
An interrupt request input
(INTTM000/INTTM010), however, is generated at the rise of the next count clock.
(10) Compare operation
A capture operation may not be performed for CR000/CR010 set in compare mode even if a capture trigger has
been input.
(11) Edge detection
<1>
If the TI000 or TI010 pin is high level immediately after system reset and the rising edge or both the rising
and falling edges are specified as the valid edge of the TI000 or TI010 pin to enable the 16-bit timer counter
00 (TM00) operation, a rising edge is detected immediately after the operation is enabled.
Be careful
therefore when pulling up the TI000 or TI010 pin. However, if the TI000 pin or TI010 pin is high level when
re-enabling operation after the operation has been stopped, the rising edge is not detected.
<2>
The sampling clock used to eliminate noise differs when the TI000 valid edge is used as the count clock
and when it is used as a capture trigger. In the former case, the count clock is fX, and in the latter case the
count clock is selected by prescaler mode register 00 (PRM00). The capture operation is only performed
when a valid level is detected twice by sampling the valid edge, thus eliminating noise with a short pulse
width.