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CHAPTER 8 8-BIT TIMERS H0 AND H1
User’s Manual U16315EJ3V1UD
210
Figure 8-15. Carrier Generator Mode Operation Timing (2/3)
(b) Operation when CMP01 = N, CMP11 = M
N
L
CMPn0
CMPn1
TMHEn
INTTMHn
Carrier clock
TM5n count value
00H
N
00H 01H
M
00H
N
00H 01H
M
00H
N
M
CR5n
TCE5n
TOHn
0
1
0
1
0
INTTM5n
NRZBn
NRZn
Carrier clock
00H 01H
L
00H 01H
L
00H 01H
L
00H 01H
L
INTTM5Hn
<1> <2>
<3>
<4>
<5>
<6>
<7>
8-bit timer 5n
count clock
8-bit timer Hn
count clock
8-bit timer counter
Hn count value
<1>
When TMHE1 = 0 and TCE51 = 0, 8-bit timer counter H1 operation is stopped.
<2>
When TMHE1 = 1 is set, 8-bit timer counter H1 starts a count operation. At that time, the carrier clock is held
at the inactive level.
<3>
When the count value of 8-bit timer counter H1 matches the CMP01 register value, the first INTTMH1 signal
is generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer
counter H1 is switched from the CMP01 register to the CMP11 register. 8-bit timer counter H1 is cleared to
00H.
<4>
When the count value of 8-bit timer counter H1 matches the CMP11 register value, the INTTMH1 signal is
generated, the carrier clock signal is inverted, and the compare register to be compared with 8-bit timer
counter H1 is switched from the CMP11 register to the CMP01 register. 8-bit timer counter H1 is cleared to
00H. By performing procedures <3> and <4> repeatedly, a carrier clock with duty fixed to other than 50% is
generated.
<5>
When the INTTM51 signal is generated, it is synchronized with 8-bit timer H1 count clock and output as the
INTTM5H1 signal.
<6>
A carrier signal is output at the first rising edge of the carrier clock if NRZ1 is set to 1.
<7>
When NRZ1 = 0, the TOH1 output is held at the high level and is not changed to low level while the carrier
clock is high level (from <6> and <7>, the high-level width of the carrier clock waveform is guaranteed).