
CHAPTER 2 PIN FUNCTIONS
User’s Manual U16315EJ3V1UD
42
2.3 Pin I/O Circuits and Recommended Connection of Unused Pins
Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins.
Refer to Figure 2-1 for the configuration of the I/O circuit of each type.
Table 2-2. Pin I/O Circuit Types
Pin Name
I/O Circuit Type
I/O
Recommended Connection of Unused Pins
P00/TI000
P01/TI010/TO00
P02
P03
P10/SCK10/TxD0
P11/SI10/RxD0
8-A
P12/SO10
P13/TxD6
5-A
P14/RxD6
8-A
P15/TOH0
5-A
P16/TOH1/INTP5
P17/TI50/TO50
8-A
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P20/ANI0 to P27/ANI7
9-C
Input
Connect to EVDD or EVSS.
P30/INTP1 to P32/INTP3
P33/TI51/TO51/INTP4
8-A
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P60, P61 (Mask ROM version)
13-S
P60, P61 (Flash memory version)
13-R
P62, P63 (Mask ROM version)
13-V
P62, P63 (Flash memory version)
13-W
Input:
Connect to EVSS.
Output: Leave this pin open at low-level output after clearing
the output latch of the port to 0.
P70/KR0 to P77/KR7
P120/INTP0
8-A
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
P130
3-C
Output
Leave open.
P140/PCL/INTP6
8-A
I/O
Input:
Independently connect to EVDD or EVSS via a resistor.
Output: Leave open.
RESET
2
Connect to EVDD or VDD.
XT1
Input
Connect directly to EVSS or VSS
Note 1.
XT2
16
Leave open.
AVREF
Connect directly to EVDD or VDD
Note 2.
AVSS
IC
Connect directly to EVSS or VSS.
VPP
Connect to EVSS or VSS.
Notes 1. Except for rank K and rank I products. When using rank K or rank I products, connect as follows.
<When regulator is not used (REGC pin is connected directly to VDD)>
XT1: Connect directly to EVDD or VDD.
<When regulator is used (a 1
F capacitor is connected to REGC pin)>
XT1: Connect directly to the REGC pin.
2. Connect port 2 directly to EVDD when it is used as a digital port.