參數(shù)資料
型號: UPD703204
廠商: NEC Corp.
英文描述: 32-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: 32位單晶片微控制器
文件頁數(shù): 88/98頁
文件大?。?/td> 797K
代理商: UPD703204
Preliminary Product Information U15436EJ1V0PM
88
μ
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
CSI Timing
(1) Master mode
(T
A
= –40 to +85°C, V
DD
= AV
DD
= EV
DD
= V
DD
BU = 2.2 to 2.7 V, V
SS
= AV
SS
= EV
SS
= V
SS
BU = 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle time
t
KCY1
<98>
Output
200
ns
SCKn high-/low-level width
t
KH1
,
t
KL1
<99>
Output
t
KCY1
/2 – 10
ns
SIn setup time (to SCKn
)
t
SIK1
<100>
30
ns
SIn hold time (from SCKn
)
t
KSI1
<101>
30
ns
Delay time from SCKn
to SOn output
t
KSO1
<102>
30
ns
Remark
n = 0 to 3 (V850ES/SA2), n = 0 to 4 (V850ES/SA3)
(2) Slave mode
(T
A
= –40 to +85°C, V
DD
= AV
DD
= EV
DD
= V
DD
BU = 2.2 to 2.7 V, V
SS
= AV
SS
= EV
SS
= V
SS
BU = 0 V, C
L
= 50 pF)
Parameter
Symbol
Conditions
MIN.
MAX.
Unit
SCKn cycle time
t
KCY2
<98>
Output
200
ns
SCKn high-/low-level width
t
KH2
,
t
KL2
<99>
Output
90
ns
SIn setup time (to SCKn
)
t
SIK2
<100>
50
ns
SIn hold time (from SCKn
)
t
KSI2
<101>
50
ns
Delay time from SCKn
to SOn output
t
KSO2
<102>
50
ns
Remark
n = 0 to 3 (V850ES/SA2), n = 0 to 4 (V850ES/SA3)
<101>
<102>
<100>
<98>
<99>
Hi-Z
Hi-Z
<99>
Remark
n = 0 to 3 (V850ES/SA2), n = 0 to 4 (V850ES/SA3)
SCKn (I/O)
SIn (input)
SOn (output)
Input data
Output data
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