![](http://datasheet.mmic.net.cn/370000/UPD703201_datasheet_16740720/UPD703201_28.png)
Preliminary Product Information U15436EJ1V0PM
28
μ
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
5. EXTERNAL BUS INTERFACE FUNCTION
The V850ES/SA2 and V850ES/SA3 incorporate an external bus interface function that can be used to connect
memories, such as ROM or RAM, and peripheral I/O externally.
The external bus interface function has the following features.
{
Separate bus/multiplexed bus output selectable
{
8-bit/16-bit data bus sizing function
{
Chip select function for four spaces
{
Wait function
Programmable wait function
External wait function
{
Idle state function
{
Bus hold function
The following pins are used for the external bus interface.
Table 5-1. List of Bus Control Pins (When Multiplexed Bus Is Selected)
Bus Control Pin
Alternate Function
I/O
Function
AD0 to AD15
PDL0 to PDL15
I/O
Address/data bus
A16 to A23
Note
PDH0 to PDH7
Output
Address bus
WAIT
PCM0
Input
External wait control
CLKOUT
PCM1
Output
Internal system clock
CS0 to CS3
PCS0 to PCS3
Output
Chip select
WR0, WR1
PCT0, PCT1
Output
Write strobe signal
RD
PCT4
Output
Read strobe signal
ASTB
PCT6
Output
Address strobe signal
HLDRQ
PCM3
Input
HLDAK
PCM2
Output
Bus hold control
Note
A16 to A21 in the V850ES/SA2.
Table 5-2. List of Bus Control Pins (When Separate Bus Is Selected)
Bus Control Pin
Alternate Function
I/O
Function
AD0 to AD15
PDL0 to PDL15
I/O
Data bus
A0 to A15
P90 to P915
Output
Address bus
A16 to A23
Note
PDH0 to PDH7
Output
Address bus
WAIT
PCM0
Input
External wait control
CLKOUT
PCM1
Output
Internal system clock
CS0 to CS3
PCS0 to PCS3
Output
Chip select
WR0, WR1
PCT0, PCT1
Output
Write strobe signal
RD
PCT4
Output
Read strobe signal
HLDRQ
PCM3
Input
HLDAK
PCM2
Output
Bus hold control
Note
A16 to A21 in the V850ES/SA2.