參數(shù)資料
型號: UPD703204
廠商: NEC Corp.
英文描述: 32-BIT SINGLE-CHIP MICROCONTROLLERS
中文描述: 32位單晶片微控制器
文件頁數(shù): 57/98頁
文件大?。?/td> 797K
代理商: UPD703204
Preliminary Product Information U15436EJ1V0PM
57
μ
PD703201, 703201Y, 703204, 703204Y, 70F3201, 70F3201Y, 70F3204, 70F3204Y
19.2 Instruction Set (In Alphabetical Order)
(1/6)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
Z SAT
reg1,reg2
rrrrr001110RRRRR
GR[reg2]
GR[reg2]+GR[reg1]
1
1
1
×
×
×
×
ADD
imm5,reg2
r r r r r 0 1 0 0 1 0 i i i i i
GR[reg2]
GR[reg2]+sign-extend(imm5)
1
1
1
×
×
×
×
ADDI
imm16,reg1,reg2
rrrrr110000RRRRR
i i i i i i i i i i i i i i i i
GR[reg2]
GR[reg1]+sign-extend(imm16)
1
1
1
×
×
×
×
AND
reg1,reg2
rrrrr001010RRRRR
GR[reg2]
GR[reg2]AND GR[reg1]
1
1
1
0
×
×
ANDI
imm16,reg1,reg2
rrrrr110110RRRRR
i i i i i i i i i i i i i i i i
GR[reg2]
GR[reg1]AND zero-extend(imm16)
1
1
1
0
0
×
When conditions
are satisfied
2
Note 2
2
Note 2
2
Note 2
Bcond
disp9
ddddd1011dddcccc
Note 1
if conditions are satisfied
then PC
PC+sign-extend(disp9)
When conditions
are not satisfied
1
1
1
BSH
reg2,reg3
rrrrr11111100000
wwwww01101000010
GR[reg3]
GR[reg2] (23 : 16) ll GR[reg2] (31 : 24) ll
GR[reg2] (7 : 0) ll GR[reg2] (15 : 8)
1
1
1
×
0
×
×
BSW
reg2,reg3
rrrrr11111100000
wwwww01101000000
GR[reg3]
GR[reg2] (7 : 0) ll GR[reg2] (15 : 8) ll GR
[reg2] (23 : 16) ll GR[reg2] (31 : 24)
1
1
1
×
0
×
×
CALLT
imm6
0 0 0 0 0 0 1 0 0 0 i i i i i i
CTPC
PC+2(return PC)
CTPSW
PSW
adr
CTBP+zero-extend(imm6 logically shift left by 1)
PC
CTBP+zero-extend(Load-memory(adr,Half-word))
4
4
4
bit#3, disp16[reg1]
10bbb111110RRRRR
dddddddddddddddd
adr
GR[reg1]+sign-extend(disp16)
Z flag
Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,0)
3
Note 3
3
Note 3
3
Note 3
×
CLR1
reg2,[reg1]
rrrrr111111RRRRR
0000000011100100
adr
GR[reg1]
Z flag
Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,0)
3
Note 3
3
Note 3
3
Note 3
×
cccc,imm5,reg2,reg3
r r r r r 1 1 1 1 1 1 i i i i i
wwwww011000cccc0
if conditions are satisfied
then GR[reg3]
sign-extended(imm5)
else GR[reg3]
GR[reg2]
1
1
1
CMOV
cccc,reg1,reg2,reg3
rrrrr111111RRRR
wwwww011001cccc0
if conditions are satisfied
then GR[reg3]
GR[reg1]
else GR[reg3]
GR[reg2]
1
1
1
reg1,reg2
rrrrr001111RRRRR
result
GR[reg2]–GR[reg1]
1
1
1
×
×
×
×
CMP
imm5,reg2
r r r r r 0 1 0 0 1 1 i i i i i
result
GR[reg2]–sign-extend(imm5)
1
1
1
×
×
×
×
CTRET
0000011111100000
0000000101000100
PC
CTPC
PSW
CTPSW
3
3
3
R
R
R
R
R
DBRET
0000011111100000
0000000101000110
PC
DBPC
PSW
DBPSW
3
3
3
R
R
R
R
R
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