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參數(shù)資料
| 型號： | UPD6708CX |
| 廠商： | NEC Corp. |
| 英文描述： | IEBusa Inter Equipment Busa PROTOCOL CONTROL LSI |
| 中文描述： | IEBusa設(shè)備布薩間協(xié)議控制大規(guī)模集成電路 |
| 文件頁數(shù)： | 14/72頁 |
| 文件大?。?/td> | 292K |
| 代理商： | UPD6708CX |
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14
μ
PD6708
(7)
Parity bits
Parity bits are used to check that there is no error in the transfer data.
A parity bit is added to the master address bits, slave address bits, control bits, message length bits, and data bits.
Even parity is used. If the number of the bits that are ‘1’ bits in data is odd, the parity bit is ‘1’, and if the number of the
bits that are ‘1’ bits is even, the parity bit is ‘0’.
(8)
Acknowledge bits
In ordinary communication (between two units), an acknowledge bit is added to the following places to confirm that data
has been acknowledged correctly.
At the end of the slave address field.
At the end of the control field.
At the end of the message length field.
At the end of a data field.
The definition of the acknowledge bit is as follows.
‘0’: Indicates that transfer data has been acknowledged (ACK).
‘1’: Indicates that transfer data has not been acknowledged (NAK).
Note that the value of the acknowledge bit is ignored in broadcast communication.
<1> Acknowledge bit at the end of the slave field
When any of the following conditions is met, the acknowledge bit at the end of the slave field is NAK, and
communication is discontinued.
If the parity of the master address bits or slave address bits is incorrect.
If a timing error (error in bit format) occurs.
If the slave unit does not exist.
<2> Acknowledge bit at the end of the control field
When any of the following conditions is met, the acknowledge bit at the end of the control field is NAK, and
communication is discontinued.
If the parity of the control bits is incorrect.
If bit 3 of the control bits is ‘1’ (write operation) when the slave receive buffer
Note
is not empty.
If the control bits indicate read operation (3H or 7H) when the slave transmit buffer
Note
is empty.
If 3H, 6H, 7H, AH, BH, EH, or FH of control bits is requested from a unit other than the unit which set the lock when
a lock has been set.
If the control bits indicate lock address read (4H) when a lock has not been set.
If a timing error occurs.
If the control bits are undefined.
Note
See
2.4 (1)
“
Reading slave status (SSR) (control bit: 0H, 6H)
”.
#
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| UPD6708GS | 制造商:NEC 制造商全稱:NEC 功能描述:IEBusa Inter Equipment Busa PROTOCOL CONTROL LSI |
| UPD6708GS(A) | 制造商:Renesas Electronics Corporation 功能描述: |
| UPD67100 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| UPD67101 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
| UPD67240 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:ASIC |
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