參數(shù)資料
型號： UDA1350AH
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： IEC 958 audio DAC(IEC 958音頻轉(zhuǎn)換器)
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù)： 26/36頁
文件大?。?/td> 154K
代理商： UDA1350AH
1999 Dec 16
26
Philips Semiconductors
Preliminary specification
IEC 958 audio DAC
UDA1350AH
Notes
1.
2.
All supply pins V
DD
and V
SS
must be connected to the same external power supply unit.
When the DAC must drive a higher capacitive load (above 50 pF), then a series resistor of 100
must be used in
order to prevent oscillations in the output stage of the operational amplifier.
The output voltage of the DAC is proportional to the DAC power supply voltage.
3.
12 TIMING CHARACTERISTICS
V
DDD
= V
DDA
= 2.7 to 3.6 V; T
amb
=
40 to +85
°
C; R
L
= 5 k
; all voltages measured with respect to ground; unless
otherwise specified.
IEC 958 inputs
V
i(p-p)
AC input voltage
(peak-to-peak value)
input resistance
hysteresis voltage
0.2
0.5
3.3
V
R
i
V
hys
6
40
k
mV
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Device reset
t
rst
PLL lock time
reset active time
250
μ
s
t
lock
time to lock
f
s
= 32.0 kHz
f
s
= 44.1 kHz
f
s
= 48.0 kHz
97.0
91.0
90.0
ms
ms
ms
I
2
S-bus timing
(see Fig.8)
T
cy(BCK)
bit clock cycle time
T
s
= cycle time of sample
frequency
1
64
T
s
s
t
BCKH
t
BCKL
t
r
t
f
t
su(WS)
t
h(WS)
t
su(DATAI)
t
h(DATAI)
t
h(DATAO)
t
d(DATAO-BCK)
t
d(DATAO-WS)
bit clock HIGH time
bit clock LOW time
rise time
fall time
set-up time word select
hold time word select
set-up time data input
hold time data input
hold time data output
data output to bit clock delay
data output to word select
delay
140
140
20
10
20
0
0
280
280
20
20
80
80
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
SYMBOL
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
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UDA1350ATS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:IEC 958 audio DAC
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