參數(shù)資料
型號(hào): UDA1350AH
廠商: NXP SEMICONDUCTORS
元件分類: 消費(fèi)家電
英文描述: IEC 958 audio DAC(IEC 958音頻轉(zhuǎn)換器)
中文描述: SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù): 16/36頁(yè)
文件大?。?/td> 154K
代理商: UDA1350AH
1999 Dec 16
16
Philips Semiconductors
Preliminary specification
IEC 958 audio DAC
UDA1350AH
8.7
L3 interface
8.7.1
G
ENERAL
The UDA1350AH has an L3 microcontroller interface and
all the digital sound processing features and various
system settings can be controlled by a microcontroller.
The controllable settings are:
Restoring L3 defaults
Power-on
Selection of input channel, clock source, DAC input and
external input format
Selection of filter mode and settings of treble and bass
boost
Volume settings
Selection of soft mute via cosine roll-off (only effective in
L3 control mode) and bypass of auto mute
Selection of de-emphasis.
The readable settings are:
Mute status of interpolator
PLL locked
SPDIF input signal locked
Audio Sample Frequency (ASF)
Valid PCM data detected
Pre-emphasis of the IEC 958 input signal
ACcuracy of the Clock (ACC).
The exchange of data and control information between the
microcontroller and the UDA1350AH is accomplished
through a serial hardware L3 interface comprising the
following pins:
L3DATA: data line
L3MODE: mode line
L3CLK: clock line.
The exchange of bytes via the L3 interface is LSB first.
The L3 format has two modes of operation:
Address mode
Data transfer mode.
The address mode is used to select a device for a
subsequent data transfer. The address mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 bits (see Fig.6).
The data transfer mode is characterized by L3MODE
being HIGH and is used to transfer one or more bytes
representing a register address, instruction or data.
Basically two types of data transfers can be defined:
Write action: data transfer
to
the device
Read action: data transfer
from
the device.
Remark:
when the device is powered up, at least one
L3CLOCK pulse must be given to the L3 interface to
wake-uptheinterfacebeforestartingsendingtothedevice
(see Fig.6). This is only needed once after the device is
powered up.
8.7.2
D
EVICE ADDRESSING
The device address consists of one byte with:
Bits 0 and 1 (called DOM bits) representing the type of
data transfer (see Table 5)
Bits 2 to 7 (address bits) representing a 6-bit device
address.
Table 5
Selection of data transfer
8.7.3
R
EGISTER ADDRESSING
After sending the device address, including Data
Operating Mode (DOM) bits indicating whether the
information is to be read or written, one data byte is sent
using bit 0 to indicate whether the information will be read
or written and bits 1 to 7 for the destination register
address.
Basically there are three methods for register addressing:
1.
Addressing for write data: bit 0 is logic 0 indicating a
write action to the destination register, followed by
bits 1 to 7 indicating the register address (see Fig.6).
2.
Addressing for prepare read: bit 0 is logic 1 indicating
that data will be read from the register (see Fig.7).
3.
Addressingfordatareadaction:inthiscasethedevice
returns a register address prior to sending data from
that register. When bit 0is logic 0, theregister address
is valid; in case bit 0 is logic 1 the register address is
invalid.
DOM
TRANSFER
BIT 0
BIT 1
0
1
0
1
0
0
1
1
not used
not used
write data or prepare read
read data
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