參數(shù)資料
型號(hào)： UDA1350AH
廠商： NXP SEMICONDUCTORS
元件分類： 消費(fèi)家電
英文描述： IEC 958 audio DAC(IEC 958音頻轉(zhuǎn)換器)
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP44
封裝： 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁(yè)數(shù)： 11/36頁(yè)
文件大?。?/td> 154K
代理商： UDA1350AH
1999 Dec 16
11
Philips Semiconductors
Preliminary specification
IEC 958 audio DAC
UDA1350AH
8.5
Data path
The UDA1350AH data path consists of the slicer and the
IEC 958 decoder, the digital data output and input
interfaces, the audio feature processor, digital interpolator
and noise shaper and the digital-to-analog converters.
8.5.1
IEC 958
INPUT
The UDA1350AH IEC 958 decoder can select one out of
two IEC 958 input channels. An on-chip amplifier with
hysteresis amplifies the IEC 958 input signal to CMOS
level (see Fig.4).
All 24 bits of data for left and right are extracted from the
input bitstream as well as several of the IEC 958 key
channel-status bits.
The extracted key parameters are:
Pre-emphasis
Audio sample frequency
Two-channel PCM indicator
Clock accuracy.
Both the lock indicator and the key channel status bits are
accessible via the L3 interface.
The UDA1350AH supports the following sample
frequencies and data bit rates:
f
s
= 32.0 kHz, resulting in a data rate of 2.048 Mbits/s
f
s
= 44.1 kHz, resulting in a data rate of 2.8224 Mbits/s
f
s
= 48.0 kHz, resulting in a data rate of 3.072 Mbits/s.
The UDA1350AH supports timing level I, II and III as
specified by the IEC 958 standard.
8.5.2
D
IGITAL DATA OUTPUT AND INPUT INTERFACE
The digital data interface enables the exchange of digital
data to and from an external signal processing device.
The digital output and input formats are identical by
design. The possible formats are (see Fig.5):
I
2
S-bus with a word length of up to 24 bits
LSB-justified with a word length of 16 bits
LSB-justified with a word length of 20 bits
LSB-justified with a word length of 24 bits.
Important: the edge of the WS signal
must
fall on the
negative edge of the BCK signal at all times for proper
operation of the input and output interface (see Fig.8).
In the static pin control mode the format is selected by
means of pins L3MODE and L3DATA. In the L3 control
mode the format defaults to the I
2
S-bus settings and is
programmable via the L3 interface.
The IEC 958 decoder provides the pre-emphasis
information from the IEC 958 input bitstream to pins
PREEM0 and PREEM1 and to the L3 interface register.
Controlling the de-emphasis is different for the two modes:
Static pin control mode:
For IEC 958 input de-emphasis is automatically done,
but for I
2
S-bus input de-emphasis is not possible.
L3 control mode:
– IEC 958 input: bit SPDSEL must be set to logic 1 and
de-emphasis is done automatically.
– I
2
S-bus input: bit SPDSEL must be set to logic 0 and
de-emphasis can be controlled via bits DE0
and DE1.
handbook, halfpage
MGS873
15,
16
SPDIF0,
SPDIF1
75
180 pF
10 nF
UDA1350AH
Fig.4 IEC 958 input circuit and typical application.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
UDA1350ATS 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:IEC 958 audio DAC
UDA1351 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:96 kHz IEC 958 audio DAC
UDA1351H 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:96 kHz IEC 958 audio DAC
UDA1351H/N1,551 功能描述:數(shù)模轉(zhuǎn)換器- DAC 96 KHZ SPDIF DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
UDA1351H/N1,557 功能描述:數(shù)模轉(zhuǎn)換器- DAC 96 KHZ SPDIF DAC RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換器數(shù)量:1 DAC 輸出端數(shù)量:1 轉(zhuǎn)換速率:2 MSPs 分辨率:16 bit 接口類型:QSPI, SPI, Serial (3-Wire, Microwire) 穩(wěn)定時(shí)間:1 us 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-14 封裝:Tube
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