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| 型號： | TVP5160PNP |
| 廠商： | TEXAS INSTRUMENTS INC |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP128 |
| 封裝： | GREEN, PLASTIC, HTQFP-128 |
| 文件頁數(shù)： | 93/111頁 |
| 文件大?。?/td> | 1400K |
| 代理商： | TVP5160PNP |
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SLES135E
– FEBRUARY 2005 – REVISED APRIL 2011
Table 3-117. VDP Pixel Alignment
Subaddress
C2h
–C3h
Default
01Eh
Subaddress
7
6
5
4
3
2
1
0
C2h
Pixel alignment [7:0]
C3h
Reserved
Pixel alignment [9:0]
Pixel alignment [9:0]: These registers form a 10-bit horizontal pixel position from the falling edge of horizontal sync, where the VDP
controller will initiate the program from one line standard to the next line standard. For example, the previous line of teletext to the next line
of closed caption. This value must be set so that the switch occurs after the previous transaction has cleared the delay in the VDP, but early
enough to allow the new values to be programmed before the current settings are required.
The default value is 0x1E and has been tested with every standard supported here. A new value will only be needed if a custom standard is
in use.
Table 3-118. VDP Line Start
Subaddress
D6h
Default
06h
7
6
5
4
3
2
1
0
VDP line start [7:0]
VDP line start [7:0]: Sets the VDP line starting address for the global line mode register
This register has to be set properly before enabling the line mode registers. The global line mode is only active in the region defined by the
VDP line start and stop registers.
Table 3-119. VDP Line Stop
Subaddress
D7h
Default
1Bh
7
6
5
4
3
2
1
0
VDP line stop [7:0]
VDP line stop address [7:0]: Sets the VDP stop line.
Table 3-120. VDP Global Line Mode
Subaddress
D8h
Default
FFh
7
6
5
4
3
2
1
0
Global line mode [7:0]
Global line mode [7:0]: VDP processing for multiple lines set by VDP start line register D6h and stop line register D7h.
Global line mode register has the same bits definitions as the line mode register's (see Table 3-143).
General line mode will have priority over the global line mode.
Table 3-121. VDP Full Field Enable
Subaddress
D9h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Full field enable
Full field enable:
0 = Disabled full field mode(default)
1 = Enabled full field mode
This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line mode register
programmed with FFh are sliced with the definition of full field mode register at subaddress DAh. Values other than FFh in the line mode
registers allow a different slice mode for that particular line.
82
Internal Control Registers
Copyright
2005–2011, Texas Instruments Incorporated
focus.ti.com: TVP5160
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