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FEATURES
APPLICATIONS
DESCRIPTION
TVP7000
SLES143 – SEPTEMBER 2005
TRIPLE 8/10-BIT, 150/110 MSPS, VIDEO
AND GRAPHICS DIGITIZER WITH ANALOG PLL
LCD TV/Monitors/Projectors
Analog Channels
DLP TV/Projectors
– -6 dB to 6 dB Analog Gain
PDP TV/Monitors
– Analog Input MUXs
PCTV Set-Top Boxes
– Auto Video Clamp
Digital Image Processing
– Three Digitizing Channels, Each With
Video Capture/Video Editing
Independently Controllable Clamp, PGA,
Scan Rate/Image Resolution Converters
and ADC
Video Conferencing
– Clamping: Selectable Clamping Between
Video/Graphics Digitizing Equipment
Bottom Level and Mid-level
– Offset: 1024-Step Programmable RGB or
YPbPr Offset Control
TVP7000 is a complete solution for digitizing video
– PGA: 8-Bit Programmable Gain Amplifier
and graphic signals in RGB or YPbPr color spaces.
– ADC: 8/10-Bit 150/110 MSPS A/D Converter
The device supports pixel rates up to 150 MHz.
– Automatic Level Control Circuit
Therefore, it can be used for PC graphics digitizing
up to the VESA standard of SXGA (1280
× 1024)
– Composite Sync: Integrated Sync-on-Green
resolution at 75 Hz screen refresh rate, and in video
Extraction From GreenLuminance Channel
environments for the digitizing of digital TV formats,
– Support for DC and AC-Coupled Input
including HDTV up to 1080p. TVP7000 can be used
Signals
to digitize CVBS and S-Video signal with 10-bit
PLL
ADCs.
– Fully Integrated Analog PLL for Pixel Clock
The TVP7000 is powered from 3.3-V and 1.8-V
Generation
supply and integrates a triple high-performance A/D
converter with clamping functions and variable gain,
– 12-150 MHz Pixel Clock Generation From
independently programmable for each channel. The
HSYNC Input
clamping timing window is provided by an external
– Adjustable PLL Loop Bandwidth for
pulse or can be generated internally. The TVP7000
Minimum Jitter
includes analog slicing circuitry on the Y or G input to
– 5-Bit Programmable Subpixel Accurate
support sync-on-luminance or sync-on-green extrac-
Positioning of Sampling Phase
tion. In addition, TVP7000 can extract discrete
HSYNC and VSYNC from composite sync using a
Output Formatter
sync slicer.
– Support for RGB/YCbCr 4:4:4 and YCbCr
TVP7000 also contains a complete analog PLL block
4:2:2 Output Modes to Reduce Board Traces
to generate a pixel clock from the HSYNC input. Pixel
– Dedicated DATACLK Output for Easy
clock output frequencies range from 12 MHz to 150
Latching of Output Data
MHz.
System
All programming of the part is done via an indus-
– Industry-Standard Normal/Fast I2C Interface
try-standard I2C interface, which supports both read-
With Register Readback Capability
ing and writing of register settings. The TVP7000 is
– Space-Saving TQFP-100 Pin Package
available in a space-saving TQFP 100-pin PowerPAD
package.
– Thermally-Enhanced PowerPAD Package
for Better Heat Dissipation
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Copyright 2005, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.