參數(shù)資料
型號： TVP5160PNP
廠商： TEXAS INSTRUMENTS INC
元件分類： 顏色信號轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP128
封裝： GREEN, PLASTIC, HTQFP-128
文件頁數(shù)： 87/111頁
文件大小： 1400K
代理商： TVP5160PNP
SLES135E
– FEBRUARY 2005 – REVISED APRIL 2011
Table 3-104. Weak Signal High Threshold
Subaddress
96h
Default
50h
7
6
5
4
3
2
1
0
Level [7:0]
This register controls the lower threshold of the noise measurement that determines whether the input signal is considered a weak signal.
Table 3-105. Status Request
Subaddress
97h
Default
00h
7
6
5
4
3
2
1
0
Reserved
Capture
Capture:
Setting a 1b in this bit causes the internal processor to capture the current settings of the AGC status, 3DNR noise measurement, and
the vertical line count registers. Because this capture is not immediate, it is necessary to check for completion of the capture by reading
the Capture bit repeatedly after setting it and waiting for it to be cleared by the internal processor. Once the Capture bit is 0b, then the
AGC status, noise measurement, and vertical line counters (3Ch/3Dh, 64h/65h, and 9Ah/9Bh) will have been updated and can be
safely read in any order.
Table 3-106. 3DYC NTSC VCR Threshold
Subaddress
98h
Default
10h
7
6
5
4
3
2
1
0
Thresh [7:0]
This register controls how 3DYC is enabled/disabled for VCR modes.
Table 3-107. 3DYC PAL VCR Threshold
Subaddress
99h
Default
20h
7
6
5
4
3
2
1
0
Thresh [7:0]
This register controls how 3DYC is enabled/disabled for VCR modes.
Table 3-108. Vertical Line Count
Subaddress
9Ah
–9Bh
Read only
Subaddress
7
6
5
4
3
2
1
0
9Ah
Vertical line [7:0]
9Bh
Reserved
Vertical line [9:8]
Vertical line [9:0] represent the detected a total number of lines from the previous frame. This can be used with nonstandard video signals
such as a VCR in trick mode to synchronize downstream video circuitry.
Because this register is a double-byte register it is necessary to capture the setting into the register to ensure that the value is not updated
between reading the lower and upper bytes. To cause this register to capture the current settings bit 0 of I2C register 97h (status request)
must be set to a 1b. Once the internal processor has updated this register, bit 0 of register 97h is cleared, indicating that both bytes of the
vertical line count register have been updated and can be read. Either byte may be read first, because no further update will occur until bit 0
of 97h is set to 1b again.
Copyright
2005–2011, Texas Instruments Incorporated
Internal Control Registers
77
focus.ti.com: TVP5160
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