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| 型號： | TSB14C01AI |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| 中文描述： | 5V的電機及電子學工程師聯(lián)合會1394-1995背板收發(fā)器/仲裁者 |
| 文件頁數(shù)： | 5/31頁 |
| 文件大小： | 424K |
| 代理商： | TSB14C01AI |
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TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
5
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
PM
HV
TYPE
I/O
DESCRIPTION
áááááááááááááááááááááááááááááá
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á
á
á
á
á
á
á
á
á
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á
á
á
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á
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á
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á
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áááááááááááááááááááááááááááááá
áááá
ááááááááá
ENA_PRI
áááááááááá
áááá
ááááááááá
áááá
áááá
ááááááááá
EX_ID5 – EX_ID0
áááááááááááá
áááá
á
á
á
á
á
á
áá
áá
32,33,34,
35,36,37
á
á
áá
áá
áá
áá
ááááááááááááááááááááá
TTL
áááááááááááááááááááááá
áá
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áá
áá
áááááááááááááááááááááá
áááááááááááááááááááááá
4,8,17,
22,38,48,
66
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ááááááááááááááááááá
áááááááááááááááááááá
ááááááááááááááááááá
ááááááááááááááááááá
ááááááááááááááááááá
áááááááááááááááááááá
á
á
á
á
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á
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á
operation, PTEST_INDRV should be tied to VCC to disable the drivers.
á
á
á
á
á
for test and debug. It can be put into a high-impedance state by
PTEST_INDRV. This terminal is not used in normal operation and is
á
á
4
á
á
á
20,21,22,
á
á
á
27,28,
29,30
áá
á
23, 24
á
á
I
á
á
á
I
á
á
á
á
á
á
á
I
á
á
á
á
I
TTL
á
between the TSB14C01A and the link layer.
Enable priority. ENA_PRI is tied low to enable the 7-bit bus request. See
I/O
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Control I/O. These are bidirectional signals that communicate between the
TSB14C01A and the link that controls passage of information between the
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á
14
áá
áá
áá
64
áá
á
á
á
á
á
á
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á
Table 1). This terminal should be tied low when not used.
External ID. The ID for this node is determined by the value on the EX_ID
is set externally by EX_ID. When this terminal is tied/driven low, the
source of the ID comes from the internal ID register.
á
Enable external ID. When EN_EXID is asserted high, the ID for this node
á
á
á
19
á
á
31
á
á
TTL
á
I
á
á
Enable external priority. When EN_EXPRI is asserted high (external
priority enabled) the priority level for this node is set externally (see
TTL
á
á
á
á
59,61,62
á
13,15,19,
29,46,53
á
41,42
áá
á
áá
á
á
áááááááááááááááá
áááááááááááááááá
the EX_PRI terminals. See Table 1 for more information.
á
External priority. The priority for this node is determined by the values on
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áááá
áááá
áááááááááááááááááááááááááááááá
áááá
ááááááááááááá
áááá
áááá
áááá
ááááááááááááááááááááááááááááááá
N_POR
áááá
áááá
áááá
áááá
RDATA
á
á
GND
á
áá
áá
18
á
á
56–60,
65,68
áá
áá
TTL
á
á
Supply
á
—
á
á
Circuit ground
LREQ
8
á
á
á
á
6
á
á
á
á
43
á
á
á
áá
á
áá
á
á
áááááááááááááááááá
áááááááááááááááá
the external driver for TDATA and TSTRB.
á
Circuit power
á
á
á
áá
16
áá
áá
áá
áá
55
áá
áá
á
á
áá
TTL
áá
GND
áá
áá
á
á
á
á
á
Not connected. These terminals must be left floating.
á
á
á
á
á
Logic reset input . Forcing N_POR low causes a reset condition and
resets the internal logic to the reset start state.
á
External driver enable. N_OEB_D is a negative active signal that enables
á
á
á
áá
áá
áá
TTL
á
á
be put into a high-impedance state by PTEST_INDRV. This terminal is not
used in normal operation.
then it should be pulled to ground. It should not be left floating
.
operating frequency is 50 MHz. When the operating frequency is 100 MHz
á
á
á
2
á
á
12
á
á
TTL
á
test terminals ARB_CLK, PHYENA, and RPREFIX. During normal
O
Phy enable. When the phy is driving it is low, PHYENA is the control to the
CTL0, CTL1, D0, and D1 drivers. PHYENA is for test and debug. It can
á
á
á
á
á
Receive data. Incoming data is received at the data rate.
á
Test output enable. PTEST_INDRV enables/disables the drivers to the
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