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| 型號： | TSB14C01AI |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| 中文描述： | 5V的電機(jī)及電子學(xué)工程師聯(lián)合會1394-1995背板收發(fā)器/仲裁者 |
| 文件頁數(shù)： | 28/31頁 |
| 文件大?。?/td> | 424K |
| 代理商： | TSB14C01AI |
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TSB14C01A, TSB14C01AI, TSB14C01AM
5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER
SGLS107A – FEBRUARY 1999 – REVISED NOVEMBER 1999
28
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
bus reset
Once a phy control request of bus reset is communicated from the node controller to the phy, the registers and
CSRs associated with the operation of that phy are initialized to their default values. State machines associated
with phy operations can be initialized. The phy communicates a BUS_RESET onto the bus. After the
BUS_RESET event is detected by the node transmitting it (i.e., approximately 320 arbitration clock times after
the signal is initiated), the phy initializes itself.
NOTE
Since a phy transmitting a BUS_RESET must also react accordingly once the BUS_RESET event
is detected, its state machines do have the opportunity to advance beyond those of other nodes.
This ensures that all nodes are in somewhat similar states after such a bus reset event. Obviously,
the logic (e.g., counters) used within the phy to generate the BUS_RESET signal must not be reset
once that phy simultaneously detects its own BUS_RESET.
Once a phy detects that a BUS_RESET event has occurred on the bus, it initializes itself. The node controller
initiates a bus reset by writing to the phy control register with the IBR bit set to 1. The phy hardware resets the
IBR bit to zero on detection of its own bus reset.
live insertion
It is up to the user to design their node or module to safely receive power from the particular backplane they
are using during a live insertion or tap-in. But in principal, live insertion is supported and does not cause a
bus-reset event to occur. Please see the TI application note, Live Insertion TI literature number SDYA012.
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| TSB14C01AMHV | Circular Connector; No. of Contacts:79; Series:MS27497; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:20; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:20-35 RoHS Compliant: No |
| TSB14C01AM | 5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSSOP-56 | Fairchild Semiconductor Product Package Material Disclosure |
| TSSOP-8PIN | Package Dimensions |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TSB14C01AIPM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB14C01AM | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB14C01AMHV | 制造商:TI 制造商全稱:Texas Instruments 功能描述:5-V IEEE 1394-1995 BACKPLANE TRANSCEIVER/ARBITER |
| TSB14C01APM | 功能描述:1394 接口集成電路 5V 50/100Mbps Backplane PLC RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
| TSB14C01APMG4 | 功能描述:1394 接口集成電路 5V 50/100Mbps Backplane PLC RoHS:否 制造商:Texas Instruments 類型:Link Layer Controller 工作電源電壓: 封裝 / 箱體:LQFP 封裝:Tray |
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