參數(shù)資料
型號: TPA5050_07
廠商: Texas Instruments, Inc.
英文描述: STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL
中文描述: 立體聲數(shù)字音頻口形同步延遲與I2C控制
文件頁數(shù): 5/21頁
文件大?。?/td> 782K
代理商: TPA5050_07
www.ti.com
Serial Audio Input Ports
over recommended operating conditions (unless otherwise noted)
th1
tsu1
tsu2
th2
DATA
BCLK
(Input)
LRCLK
(Input)
APPLICATION INFORMATION
AUDIO SERIAL INTERFACE
The audio serial interface for the TPA5050 consists of a 3-wire synchronous serial port. It includes LRCLK,
BCLK, and DATA. BCLK is the serial audio bit clock, and it is used to clock the serial data present on DATA into
the serial shift register of the audio interface. Serial data is clocked into the TPA5050 on the rising edge of
BCLK. LRCLK is the serial audio left/right word clock. It is used to latch serial data into the internal registers of
the serial audio interface. LRCLK is operated at the sampling frequency, fs. BCLK can be operated at 32 to 64
times the sampling frequency for right-justified, left-justified, and I
2
S formats. A system clock is not necessary for
the operation of the TPA5050.
AUDIO DATA FORMATS AND TIMING
The TPA5050 supports industry-standard audio data formats, including right-justified, I
2
S, and left-justified. The
data formats are shown in
Figure 4
. Data formats are selected using the I
2
C interface and register map (see
Table 1
).
TPA5050
SLOS492B–MAY 2006–REVISED MAY 2007
TEST CONDITIONS
MIN
1.024
TYP
MAX
12.288
UNIT
MHz
ns
ns
ns
ns
kHz
f
SCLKIN
Frequency, BCLK 32
×
fs, 48
×
fs, 64
×
fs
t
su1
Setup time, LRCLK to BCLK rising edge
t
h1
Hold time, LRCLK from BCLK rising edge
t
su2
Setup time, DATA to BCLK rising edge
t
h2
Hold time, DATA from BCLK rising edge
LRCLK frequency
BCLK duty cycle
LRCLK duty cycle
BCLK rising edges between LRCLK rising edges
10
10
10
10
32
48
192
50%
50%
LRCLK duty cycle = 50%
32
64
BCLK edges
Figure 3. Serial Data Interface Timing
5
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