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參數(shù)資料
| 型號： | TPA5050_07 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL |
| 中文描述： | 立體聲數(shù)字音頻口形同步延遲與I2C控制 |
| 文件頁數(shù)： | 13/21頁 |
| 文件大?。?/td> | 782K |
| 代理商： | TPA5050_07 |
www.ti.com
Single Byte Read
D2
Start
ACK
01
ACK
Start
D3
XX
TPA5050 Address and
Write
Register Address
(Control Register)
Stop
ACK
Data Read
(Control Register)
No
ACK
TPA5050 Address and
Read
Multiple Byte Read
XX
ACK
XX
XX
XX
Data Read
(Frame Delay)
Data Read
(Left Delay Upper)
ACK
ACK
XX
ACK
Data Read
(Right Delay Lower)
D2
Start
ACK
01
Start
ACK
D3
TPA5050 Address and
Read
Register Address
(Control Register)
ACK
XX
ACK
XX
Data Read
(Control Register)
TPA5050 Address and
Write
ACK
XX
Stop
No
ACK
Data Read
(Complete Update)
Data Read
(Left Delay Lower)
Data Read
(RJ Packet Length)
ACK
Data Read
(Right Delay Upper)
TPA5050
SLOS492B–MAY 2006–REVISED MAY 2007
In this example, one byte of data is read from the Control Register (0x01). After the data (represented
xx
) by is
read by the master device, the master device issues a Not Acknowledge, before stopping the communication.
Often, when it is necessary to read what is contained in one register, it is necessary to determine what
information is contained in all registers. In such a case, a sequential read should be used. In situations where
data must be read from a register at the beginning (0x01), and a register towards the end (0x07), a sequential
read is likely to be faster to implement than multiple single byte reads.
In this example, a sequential read is initiated with the Control Register (0x01), and ends with the Complete
Update Register (0x08).
13
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