參數(shù)資料
型號(hào): TPA5050_07
廠商: Texas Instruments, Inc.
英文描述: STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL
中文描述: 立體聲數(shù)字音頻口形同步延遲與I2C控制
文件頁(yè)數(shù): 11/21頁(yè)
文件大小: 782K
代理商: TPA5050_07
www.ti.com
RJ PACKET LENGTH REGISTERS (0x07)
This register is only used in right justified mode. The decimal value of bits [5:0] represents the width of the
useable data in a right justified audio stream. The number of BCLK transitions between LRCLK transitions must
be greater than or equal to the packet length selected in this register. The maximum packet length value is 24
bits. Any setting greater whose numerical value is greater than 24 bits is limited to the maximum 24 bits.
COMPLETE UPDATE REGISTER (0x08)
Since the audio delay values are divided among several registers, it is likely that multiple writes would be
necessary to configure the device. This may cause interruptions in the audio stream and unwanted pops and
clicks might occur as register data is passed to delay functional block.
TPA5050
SLOS492B–MAY 2006–REVISED MAY 2007
If the result of the formula above is greater than the maximum number of delay samples (8191 for TPA5050),
then the value is limited to this maximum before passing to the delay block.
Table 5. Frame Delay Registers (0x06)
(1)
D7
0
D6
D5
D4
D3
D2
D1
D0
FUNCTION
Settings in this register are masked and audio delay is determined by
settings in the right/left audio delay registers.
Right/left audio delay registers are masked and delay is determined by settings in
this register.
Frame rate = 50 Hz
Frame rate = 59.94 Hz
Audio sample rate = 32 kHz
Audio sample rate = 44.1 kHz
Audio sample rate = 48 kHz
Audio sample rate = 88.2 kHz
Audio sample rate = 96 kHz
Audio sample rate = 176.4 kHz
Audio sample rate = 192 kHz
Audio sample rate = 192 kHz
Delay frames = 1
Delay frames = 2
Delay frames = 8
1
0
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
0
0
1
0
1
1
(1)
Default values are in
bold
.
Table 6. RJ Package Length (0x07)
(1)
D5
0
0
0
D4
0
0
1
D3
0
0
1
D2
0
0
X
D1
0
0
X
D0
0
1
X
FUNCTION
Packet length = 0 bits
Packet length = 1 bits
Packet length = 24 bits
(1)
Default values are in
bold
.
To avoid this from happening, the
Complete Update
register is used to transfer the user settings from the
register file to the delay functional block when a 1 is written to the LSB. For example, if the right delay is set to
35 samples, and the left delay is set to 300 samples, the device holds the right channel in MUTE until 35
samples of audio data have passed, and holds the left channel in MUTE until 300 samples of audio data have
passed.
Note that the individual channels can be muted using the upper bits of the Control Registers
without
writing to
the Complete Update registers.
11
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