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參數(shù)資料
| 型號(hào)： | TPA5050_07 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL |
| 中文描述： | 立體聲數(shù)字音頻口形同步延遲與I2C控制 |
| 文件頁(yè)數(shù)： | 10/21頁(yè) |
| 文件大?。?/td> | 782K |
| 代理商： | TPA5050_07 |
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SERIAL CONTROL INTERFACE REGISTER SUMMARY
CONTROL REGISTER (0x01)
The control register allows the user to mute a specific audio channel. It is also used to specify the data type (I
2
S,
Right-Justified, or Left-Justified.
AUDIO DELAY REGISTERS (0x02–0x05)
The audio delay for the left and right channels is fixed by writing a total of 13 bits (2 byte transfer) to upper and
lower registers as specified in
Table 1
. A multiple byte transfer should be performed starting with the control
register and following with 4 bytes to fill the upper and lower registers associated with right/left channel delay.
The decimal value of D0–D12 equals the number of samples to delay. The maximum number of delayed
samples is 8191 for the TPA5050. This equates to 170.65 ms [8191
×
(1/fs)] at 48 kHz.
FRAME DELAY REGISTERS (0x06)
This register can be used to specify delay in video frames instead of audio samples. When the MSB is set to 1,
the audio delay registers (0x01–0x04) are bypassed and the Frame Delay Register is used to set the delay
based on the frame rate (D6), audio sample rate (D5–D3), and number of frames to delay (D2–D0).
TPA5050
SLOS492B–MAY 2006–REVISED MAY 2007
Table 2. Serial Control Register Summary
REGISTER
REGISTER NAME
NO. OF
BYTES
1
1
1
1
1
1
1
1
CONTENTS
INITIALIZATION
VALUE
00
00
00
00
00
00
00
00
0x01
0x02
0x03
0x04
0x05
0x06
0x07
0x08
Control Register
Right Delay Upper (5 bits)
Right Delay Lower (8 bits)
Left Delay Upper (5 bits)
Left Delay Lower (8 bits)
Frame Delay
RJ Packet Length
Complete Update
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Description shown in subsequent section
Table 3. Control Registers (0x01)
(1)
D7
0
0
1
1
–
–
–
–
D6
0
1
0
1
–
–
–
–
D5
X
X
X
X
X
X
X
X
D4
X
X
X
X
X
X
X
X
D3
X
X
X
X
X
X
X
X
D2
X
X
X
X
X
X
X
X
D1
–
–
–
–
0
0
1
1
D0
–
–
–
–
0
1
0
1
FUNCTION
Left and Right channel are active.
Left channel is MUTED.
Right channel is MUTED.
Left and Right channel are MUTED.
I
2
S data format
Right-justified data format (see PACKET LENGTH register 0x07)
Left-justified data format
Bypass mode – data is passed straight through without delay.
(1)
Default values are in
bold
.
Table 4. Audio Delay Registers (0x02–0x05)
(1)
D12
0
0
1
D11
0
0
1
D10–D2
0
0
1
D1
0
0
1
D0
0
1
1
FUNCTION
Left and Right audio is passed to output with no delay.
Left and Right audio is delayed by 1 sample (1/fs = delay time)
Left and Right audio is delayed by 8191 samples (8191/fs = delay time)
(1)
Default values are in
bold
.
The total audio delay time is calculated by the following formula:
Audio Delay (in samples) = int [# Delay Frames
×
(1/Frame Rate)
×
Audio Sample Rate]
10
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| TPA5050EVM | 功能描述:音頻 IC 開(kāi)發(fā)工具 AUD DELAY DEVICE RoHS:否 制造商:Texas Instruments 產(chǎn)品:Evaluation Kits 類(lèi)型:Audio Amplifiers 工具用于評(píng)估:TAS5614L 工作電源電壓:12 V to 38 V |
| TPA5050RSAR | 功能描述:音頻 DSP St Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TPA5050RSARG4 | 功能描述:音頻 DSP St Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TPA5050RSAT | 功能描述:音頻 DSP St Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
| TPA5050RSATG4 | 功能描述:音頻 DSP St Dig Aud Delay Proc RoHS:否 制造商:Texas Instruments 工作電源電壓: 電源電流: 工作溫度范圍: 安裝風(fēng)格: 封裝 / 箱體: 封裝:Tube |
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