參數(shù)資料
型號： TPA5050_07
廠商： Texas Instruments, Inc.
英文描述： STEREO DIGITAL AUDIO LIP-SYNC DELAY WITH I2C CONTROL
中文描述： 立體聲數(shù)字音頻口形同步延遲與I2C控制
文件頁數(shù)： 4/21頁
文件大?。?/td> 782K
代理商： TPA5050_07
www.ti.com
DC CHARACTERISTICS
T
A
= 25
°
C, V
DD
= 3 V (unless otherwise noted)
TIMING CHARACTERISTICS
(1)(2)
For I
2
C Interface Signals Over Recommended Operating Conditions (unless otherwise noted)
SCL
SDA
tw(H)
tw(L)
tsu1
th1
SCL
SDA
th2
t(buf)
tsu2
tsu3
Start Condition
Stop Condition
TPA5050
SLOS492B–MAY 2006–REVISED MAY 2007
PARAMETER
Supply current
High-level output current
Low-level output current
TEST CONDITIONS
MIN
TYP
1.5
MAX
UNIT
mA
mA
mA
I
DD
I
OH
I
OL
V
DD
= 3.3 V, fs = 48 kHz, BCLK = 32 fs
DATA_OUT = 2.6 V
DATA_OUT = 0.4 V
DATA, LRCLK, BCLK, SCL, SDA, Vi = 5.5V, VDD = 3V
ADD[2:0], Vi = 3.6V, VDD = 3.6V
DATA, LRCLK, BCLK, SCL, SDA, ADD[2:0], Vi = 0V,
VDD = 3.6V
3
7
7
13
13
20
5
I
IH
High-level input current
μ
A
I
IL
Low-level input current
1
μ
A
PARAMETER
TEST CONDITIONS
No wait states
MIN
TYP
MAX
400
UNIT
kHz
μ
s
μ
s
ns
ns
μ
s
μ
s
μ
s
μ
s
f
SCL
t
w(H)
t
w(L)
t
su1
t
h1
t
(buf)
t
su2
t
h2
t
su3
Frequency, SCL
Pulse duration, SCL high
Pulse duration, SCL low
Setup time, SDA to SCL
Hold time, SCL to SDA
Bus free time between stop and start condition
Setup time, SCL to start condition
Hold time, start condition to SCL
Setup time, SCL to stop condition
0.6
1.3
100
10
1.3
0.6
0.6
0.6
(1)
(2)
V
= V
A pull-up resistor
≤
2 k
is required for a 5 V I
2
C bus voltage.
Figure 1. SCL and SDA Timing
Figure 2. Start and Stop Conditions Timing
4
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TPA6204A1DGN R-78Bxx-1.0(L) Series - Innoline Regulated DC-DC Converters; Output Voltage (Vdc): 5.0V; Output Current (A): 1.0A; Features: Efficiency up to 97%,Non isolated, no need for heatsinks; Pin-out compatible with LM78XX Linears; Low profile( L*W*H=11.5*8.5*17.5mm); Wide input range.(4.75V ~ 34V); Short circuit protection, Thermal shutdown; Non standard outputs available as specialsbetween 1.5V ~15V; Low ripple and noise; ?L? version with 90?? pins
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