參數(shù)資料
型號： TP6508
英文描述： Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT
中文描述： 顯卡
文件頁數(shù)： 68/134頁
文件大?。?/td> 600K
代理商： TP6508
P.65
Extended Indexed Register CREG 24 : CRT Vertical High Register
This is a read/write register.
Port address is Hex 3D5.
Default value after hardware reset is Hex 00.
D0
D1
D2
D3
D4
D5-7 Reserved
Vertical total bit 10
Vertical display enable end bit 10
Vertical blank star bit 10
Vertical retrace start bit 10
Line compare bit 10
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5-7
Bit 10 of the vertical total register.
Bit 10 of the vertical display enable register.
Bit 10 of the vertical blank start register.
Bit 10 of the vertical retrace start register.
Bit 10 of the line compare register.
Reserved.
Extended Indexed Register CREG 25 : Half Horizontal Retrace Start Register
This is a read/write register.
Port address is Hex 3D5.
Default value after hardware reset is Hex 00.
D0-7 Half horizontal retrace start bit 0 to 7
Bit 0-7
In interlace display mode , TP6508 need a count point that point at half of a scan-line to generate the
interlace display timing sequence . And these bits are nice to program doing it , a real interlace display
.
Extended Indexed Register CREG 26 : TV Leading Horizontal Retrace Start Register
This is a read/write register.
Port address is Hex 3D5.
Default value after hardware reset is Hex 00.
D0-7 TV leading horizontal retrace start bit 0 to 7
Bit 0-7
By TV display, it was designed to base on the interlace scan technique, TP6508 need two retrace
signal(like VGA retrace signal) on even field and odd field. TV composite sync. signal waveform in-
clude two equalizing pulse interval, front and back the vertical sync. interval, those have three pulse
individually. We need to define the intervals position in the TV composite sync. waveform. So we can
use these bits to program the front equalizing pulse(front of horizontal sync. pulse interval ) start
position. on even field and make it be able using in TV display mode.
Extended Indexed Register CREG 27 : TV Horizontal Retrace End for Equalizing Pulse
Register
This is a read/write register.
Port address is Hex 3D5.
Default value after hardware reset is Hex 00.
D0-3 TV horizontal retrace end bit 0 to 3
D4-7 Reserved
Bit 0-3
These bits is used to program the back equalizing pulse(back of horizontal sync. pulse
interval ) start position. on even field and make it be able using in TV display mode.
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