參數(shù)資料
型號： TP6508
英文描述： Pushbutton Switch; Actuator Diameter:0.078"; Circuitry:6PDT; Switch Operation:6 Changeover Push-Push; Contact Current Max:100mA; Leaded Process Compatible:Yes; Mounting Type:PCB; Switch Function:6PDT
中文描述： 顯卡
文件頁數(shù)： 59/134頁
文件大?。?/td> 600K
代理商： TP6508
P.56
Bit 5
0
0
1
1
Bit 4
0
1
0
1
Data width
8-bit
16-bit
32-bit
32-bit or 16-bit
Bit 6
This bit is used to set the host-to-display memory bus width on 16 color modes. A logical 1 enables
TP6508 to expand to 16-bit data bus access. A logical 0 forces TP6508 to access in 8-bit data bus.
A logical 1 forces the pixel data bypass the internal palette and transfer through a special logical
block to do as internal palette. In high speed video clock mode , the lookup internal palette operation
is critical .
Bit 7
Extended Indexed Register SREG CD: Display Memory Register
This is a read/write register.
Port address is Hex 3C5.
Default value after hardware reset is Hex 00.
D0-1 Display memory configuration
D2
Asymmetical/symmetical address select for DRAM-A & B
D3
Dual-Write/Dual-Cas select for DRAM-A & B
D4
Asymmetical/symmetical address select for DRAM-C
D5
Dual-Write/Dual-Cas select for DRAM-C
D6
Enable 2M-byte display memory size
D7
Reserved
Bit 0-1
These bit are used to configure the DRAMs interface.
Bit 1
Bit 0
0
0
0
1
1
0
1
1
(*: DRAM-C isn't used as an external frame buffer with this setting, but does as display
memory.)
A logical 0 indicates TP6508 to support symmetical DRAM memory addressing for DRAM-A & B. A
logical 1 indicates TP6508 to support asymmetical DRAM memory addressing.
A logical 0 indicates TP6508 to support dual-CAS DRAM memory addressing for DRAM-A & B. A
logical 1 indicates TP6508 to support dual-WRITE DRAM memory addressing.
A logical 0 indicates TP6508 to support symmetical DRAM memory addressing for DRAM-C. A
logical 1 indicates TP6508 to support asymmetical DRAM memory addressing.
A logical 0 indicates TP6508 to support dual-CAS DRAM memory addressing for DRAM-C. A logi-
cal 1 indicates TP6508 to support dual-WRITE DRAM memory addressing.
A logical 1 enables TP6508 is operated on 2M-byte size memory configuration .
dition , TP6508 will adjust some of the counter length of the CRTC and size again the domain of
display memory address.
Reserved.
Display Memory Bus Width & Configuration
32-bit, Enable DRAM-A & DRAM-B interface
16-bit, Enable DRAM-A only
32-bit, Enable DRAM-A & DRAM-C interface *
Reserved
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Under the con-
Bit 7
Extended Indexed Register SREG CE: Configuration Register 1
This is a read only register.
Port address is Hex 3C5.
Default value after hardware reset is Hex FF. (Chip internal pull high during power on reset)
D0
D1
D2
Enable BIOS ROMCS* signal output from OFF pin
Enable 64k VGA BIOS decoding
Relocation VGA BIOS address
相關(guān)PDF資料
PDF描述
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