參數(shù)資料
型號(hào): TLV5592
廠商: Texas Instruments, Inc.
英文描述: 2-BIT ANALOG-TO-DIGITAL CONVERTER FOR FLEX PAGER CHIPSET
中文描述: 2位模擬數(shù)字轉(zhuǎn)換器對(duì)于Flex尋呼機(jī)芯片組
文件頁(yè)數(shù): 3/15頁(yè)
文件大?。?/td> 208K
代理商: TLV5592
TLV5592
2-BIT ANALOG-TO-DIGITAL CONVERTER
FOR FLEX PAGER CHIPSET
SLAS145A – JUNE1996 – REVISED DECEMBER 1997
3
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
Terminal Functions
TERMINAL
NAME
I/O
DESCRIPTION
NO.
AVDD
BW
2
I
Analog supply voltage
7
I
Digital bandwidth select. A high level on BW selects the 2-kHz filter cutoff and a low level selects the 1-kHz
filter cutoff.
CON1
8
I
Digital control 1 input. In conjunction with CON2, CON1 selects fast track, slow track, hold, or standby mode.
CON2
9
I
Digital control 2 input. In conjunction with CON1, CON2 selects fast track, slow track, hold, or standby mode.
CLK
14
I
Digital clock input. CLK input is a 50% duty cycle transistor-transistor logic (TTL)-level clock input with nominal
frequency of 38.4 kHz. The CLK input is edge sensitive in all non-test modes. For all test modes, the CLK input
is level sensitive.
DC OFFSET
4
I
Analog dc offset correction input. The dc component of the audio signal should be applied to DC OFFSET.
DVDD
EXTS0
1
I
Digital supply voltage
11
O
Digital output 0 of the ADC. Data bit 0 is the least significant bit (LSB).
EXTS1
10
O
Digital output 1 of the ADC. Data bit 1 is the most significant bit (MSB).
GND
6
Return terminal for the IC current
MID
5
O
Analog midpoint output. MID is a buffered output of AVDD/2.
Analog audio signal input. An appropriate resistance capacitance (RC) low-pass filter (antialiasing filter)
should be connected to SIG.
SIG
3
I
TEST
13
I
Digital test input enable. TEST should be connected to ground in normal operation.
TRACKINH
12
I
Digital track inhibit logic input. A high level on TRACKINH disables the peak and valley detector counters; a
low level enables the peak and valley detector counters. The counters continue to decay at the decay rate while
TRACKINH is a low level.
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