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參數(shù)資料
| 型號： | TLV5592 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | 2-BIT ANALOG-TO-DIGITAL CONVERTER FOR FLEX PAGER CHIPSET |
| 中文描述： | 2位模擬數(shù)字轉(zhuǎn)換器對于Flex尋呼機(jī)芯片組 |
| 文件頁數(shù)： | 10/15頁 |
| 文件大?。?/td> | 208K |
| 代理商： | TLV5592 |
TLV5592
2-BIT ANALOG-TO-DIGITAL CONVERTER
FOR FLEX PAGER CHIPSET
SLAS145A – JUNE1996 – REVISED DECEMBER 1997
10
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
The thresholds for the ADC comparators are set by capacitor ratios in switched-capacitor comparators. For a
2-bit ADC, three comparators are used with thresholds set as shown in Table 3.
Table 3. Comparators and Associated Threshold Values (see Notes 4 and 5)
COMPARATOR
VALUE
UNIT
V
Lower threshold
((peak – valley) x 50/256) + valley
Middle threshold
((peak – valley) x 134/256) + valley
V
Upper threshold
((peak – valley) x 217/256) + valley
V
NOTES:
4. The constants 50/256, 134/256, and 217/256 have a
±
5% tolerance.
5. The comparator thresholds are measured with the input voltage level of the SIG terminal at 125 mV
ac centered on 800 mV dc, and the input voltage at the DC OFFSET terminal is 800 mV dc.
peak and valley timing
The peak and valley attack and delay times are controlled by two 8-bit up-down counters clocked by the CLK
input. The rate that the counters are clocked depends on whether the counters are in attack or decay mode.
The peak counter is in attack mode when the input signal amplitude is greater than the output voltage from the
peak DAC, and it is in decay mode when the input signal amplitude is less that the peak DAC output voltage.
The valley counter is in attack mode when the input signal amplitude is less than the output voltage from the
valley DAC, and it is in decay mode when the input signal amplitude is greater than the valley DAC output
voltage.
When TRACKINH is held high, the attack and decay enable inputs to the peak and valley counters are disabled.
When TRACKINH is held low, the attack and decay enable inputs to the peak and valley counters are enabled.
The effect of the TRACKINH signal is exactly the same as when the device is configured in hold mode.
slow track mode attack and decay times
The attack rate is calculated equal to [V
DD
×
f
(CLK)
×
2] / 256 / (TRACKINH duty cycle). So the peak and valley
counter is incremented or decremented by 2 on every clock cycle when the input signal amplitude is greater
than or less than the peak and valley DAC output voltage.
The decay rate is calculated equal to [V
DD
×
f
(CLK)
] / (256
×
40) / (TRACKINH duty cycle). So the peak and valley
counter is decremented or incremented once every 40 clock cycles when the input signal amplitude is less than
or greater than the peak and valley DAC output voltage.
When the counters receive an attack enable at the same time as a decay enable, the attack enable takes
precedence. The decay counter is reset to 1 after an attack and reset to 40 following a decay.
The attack and decay times for a V
DD
supply variation of 1.8 V to 2.5 V and a fixed clock input of 38.4 kHz are
given in Table 4.
Table 4. Slow Track Mode Attack and Decay Times
DESCRIPTION
CONDITIONS
MIN
MAX
UNIT
Attack rate (ATTR)
TRACKINH = Low
810
990
mV/ms
Decay rate (DECR)
TRACKINH = Low
10.125
12.375
mV/ms
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
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