參數(shù)資料
型號(hào): TLV320AIC3106_0706
廠商: Texas Instruments, Inc.
元件分類: Codec
英文描述: LOW-POWER STEREO AUDIO CODEC FOR PORTABLE AUDIO/TELEPHONY
中文描述: 低功耗立體聲音頻編解碼器的便攜式音頻/電話
文件頁(yè)數(shù): 79/102頁(yè)
文件大?。?/td> 1259K
代理商: TLV320AIC3106_0706
www.ti.com
TLV320AIC3106
SLAS509B–DECEMBER 2006–REVISED JUNE 2007
Page 0 / Register 99:
GPIO2 Control Register
BIT
READ/
WRITE
R/W
RESET
VALUE
0000
DESCRIPTION
D7-D4
GPIO2 Output Control
0000: GPIO2 is disabled
0001: Reserved. Do not use.
0010: GPIO2 output = jack/headset detect interrupt (interrupt polarity: active high. Typical interrupt
duration: 1.75 ms.)
0011: GPIO2 = general purpose input
0100: GPIO2 = general purpose output
0101-0111: GPIO2 input = digital microphone input, data sampled on clock rising and falling edges
1000: GPIO2 = bit clock for audio serial data bus (programmable as input or output)
1001: GPIO2 output = Headset Detect OR Button Press Interrupt
1010: GPIO2 output = Headset Detect OR Button Press OR Short-Circuit Detect OR AGC Noise
Detect Interrupt
1011: GPIO2 output = Short Circuit Detect OR AGC Noise Detect Interrupt
1100: GPIO2 output = Headset Detect OR Button Press OR Short-Circuit Detect Interrupt
1101: GPIO2 output = Short Circuit Detect Interrupt
1110: GPIO2 output = AGC Noise Detect Interrupt
1111: GPIO2 output = Button Press / Hookswitch Interrupt
GPIO2 General Purpose Output Value
0: GPIO1 outputs a logic-low level
1: GPIO1 outputs a logic-high level
GPIO2 General Purpose Input Value
0: A logic-low level is input to GPIO2
1: A logic-high level is input to GPIO2
GPIO2 Interrupt Duration Control
0: GPIO2 Interrupt occurs as a single active-high pulse of typical duration 2ms.
1: GPIO2 Interrupt occurs as continuous pulses until the Interrupt Flags register (register 96) is read
by the host
Reserved. Don’t write to this register bit.
D3
R/W
0
D2
R
0
D1
R/W
0
D0
R
0
Page 0 / Register 100:
Additional GPIO Control Register A
BIT
READ/
WRITE
R/W
RESET
VALUE
00
DESCRIPTION
D7-D6
SDA Pin Control
(1)
The SDA pin hardware includes pull-down capability only (open-drain NMOS), so an external pull-up
resistor is required when using this pin, even in GPIO mode.
00: SDA pin is not used as general purpose I/O
01: SDA pin used as general purpose input
10: SDA pin used as general purpose output
11: Reserved. Do not write this sequence to these register bits.
SDA General Purpose Output Control
(1)
0: SDA driven to logic-low when used as general purpose output
1: SDA driven to logic-high when used as general purpose output (requires external pull-up resistor)
SDA General Purpose Input Value
(1)
0: SDA detects a logic-low when used as general purpose input
1: SDA is detects a logic-high when used as general purpose input
SCL Pin Control
(1)
The SCL pin hardware includes pulldown capability only (open-drain NMOS), so an external pull-up
resistor is required when using this pin, even in GPIO mode.
00: SCL pin is not used as general purpose I/O
01: SCL pin used as general purpose input
10: SCL pin used as general purpose output
11: Reserved. Do not write this sequence to these register bits.
SCL General Purpose Output Control
(1)
0: SCL driven to logic-low when used as general purpose output
1: SCL driven to logic-high when used as general purpose output (requires external pull-up resistor)
SCL General Purpose Input Value
(1)
0: SCL detects a logic-low when used as general purpose input
1: SCL detects a logic-high when used as general purpose input
D5
R/W
0
D4
R
0
D3-D2
R/W
00
D1
R/W
0
D0
R
0
(1)
The control bits in Register 100 are only valid in SPI Mode, when SELECT=1.
79
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